xref: /openbmc/u-boot/arch/arm/dts/meson-gxbb.dtsi (revision cbd2fba1) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Andreas Färber
4 */
5
6#include "meson-gx.dtsi"
7#include <dt-bindings/gpio/meson-gxbb-gpio.h>
8#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
9#include <dt-bindings/clock/gxbb-clkc.h>
10#include <dt-bindings/clock/gxbb-aoclkc.h>
11#include <dt-bindings/reset/gxbb-aoclkc.h>
12
13/ {
14	compatible = "amlogic,meson-gxbb";
15
16	soc {
17		usb0_phy: phy@c0000000 {
18			compatible = "amlogic,meson-gxbb-usb2-phy";
19			#phy-cells = <0>;
20			reg = <0x0 0xc0000000 0x0 0x20>;
21			resets = <&reset RESET_USB_OTG>;
22			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
23			clock-names = "usb_general", "usb";
24			status = "disabled";
25		};
26
27		usb1_phy: phy@c0000020 {
28			compatible = "amlogic,meson-gxbb-usb2-phy";
29			#phy-cells = <0>;
30			reg = <0x0 0xc0000020 0x0 0x20>;
31			resets = <&reset RESET_USB_OTG>;
32			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
33			clock-names = "usb_general", "usb";
34			status = "disabled";
35		};
36
37		usb0: usb@c9000000 {
38			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
39			reg = <0x0 0xc9000000 0x0 0x40000>;
40			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
41			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
42			clock-names = "otg";
43			phys = <&usb0_phy>;
44			phy-names = "usb2-phy";
45			dr_mode = "host";
46			status = "disabled";
47		};
48
49		usb1: usb@c9100000 {
50			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
51			reg = <0x0 0xc9100000 0x0 0x40000>;
52			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
53			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
54			clock-names = "otg";
55			phys = <&usb1_phy>;
56			phy-names = "usb2-phy";
57			dr_mode = "host";
58			status = "disabled";
59		};
60	};
61};
62
63&aobus {
64	pinctrl_aobus: pinctrl@14 {
65		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
66		#address-cells = <2>;
67		#size-cells = <2>;
68		ranges;
69
70		gpio_ao: bank@14 {
71			reg = <0x0 0x00014 0x0 0x8>,
72			      <0x0 0x0002c 0x0 0x4>,
73			      <0x0 0x00024 0x0 0x8>;
74			reg-names = "mux", "pull", "gpio";
75			gpio-controller;
76			#gpio-cells = <2>;
77			gpio-ranges = <&pinctrl_aobus 0 0 14>;
78		};
79
80		uart_ao_a_pins: uart_ao_a {
81			mux {
82				groups = "uart_tx_ao_a", "uart_rx_ao_a";
83				function = "uart_ao";
84			};
85		};
86
87		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
88			mux {
89				groups = "uart_cts_ao_a",
90				       "uart_rts_ao_a";
91				function = "uart_ao";
92			};
93		};
94
95		uart_ao_b_pins: uart_ao_b {
96			mux {
97				groups = "uart_tx_ao_b", "uart_rx_ao_b";
98				function = "uart_ao_b";
99			};
100		};
101
102		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
103			mux {
104				groups = "uart_cts_ao_b",
105				       "uart_rts_ao_b";
106				function = "uart_ao_b";
107			};
108		};
109
110		remote_input_ao_pins: remote_input_ao {
111			mux {
112				groups = "remote_input_ao";
113				function = "remote_input_ao";
114			};
115		};
116
117		i2c_ao_pins: i2c_ao {
118			mux {
119				groups = "i2c_sck_ao",
120				       "i2c_sda_ao";
121				function = "i2c_ao";
122			};
123		};
124
125		pwm_ao_a_3_pins: pwm_ao_a_3 {
126			mux {
127				groups = "pwm_ao_a_3";
128				function = "pwm_ao_a_3";
129			};
130		};
131
132		pwm_ao_a_6_pins: pwm_ao_a_6 {
133			mux {
134				groups = "pwm_ao_a_6";
135				function = "pwm_ao_a_6";
136			};
137		};
138
139		pwm_ao_a_12_pins: pwm_ao_a_12 {
140			mux {
141				groups = "pwm_ao_a_12";
142				function = "pwm_ao_a_12";
143			};
144		};
145
146		pwm_ao_b_pins: pwm_ao_b {
147			mux {
148				groups = "pwm_ao_b";
149				function = "pwm_ao_b";
150			};
151		};
152
153		i2s_am_clk_pins: i2s_am_clk {
154			mux {
155				groups = "i2s_am_clk";
156				function = "i2s_out_ao";
157			};
158		};
159
160		i2s_out_ao_clk_pins: i2s_out_ao_clk {
161			mux {
162				groups = "i2s_out_ao_clk";
163				function = "i2s_out_ao";
164			};
165		};
166
167		i2s_out_lr_clk_pins: i2s_out_lr_clk {
168			mux {
169				groups = "i2s_out_lr_clk";
170				function = "i2s_out_ao";
171			};
172		};
173
174		i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
175			mux {
176				groups = "i2s_out_ch01_ao";
177				function = "i2s_out_ao";
178			};
179		};
180
181		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
182			mux {
183				groups = "i2s_out_ch23_ao";
184				function = "i2s_out_ao";
185			};
186		};
187
188		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
189			mux {
190				groups = "i2s_out_ch45_ao";
191				function = "i2s_out_ao";
192			};
193		};
194
195		spdif_out_ao_6_pins: spdif_out_ao_6 {
196			mux {
197				groups = "spdif_out_ao_6";
198				function = "spdif_out_ao";
199			};
200		};
201
202		spdif_out_ao_13_pins: spdif_out_ao_13 {
203			mux {
204				groups = "spdif_out_ao_13";
205				function = "spdif_out_ao";
206			};
207		};
208
209		ao_cec_pins: ao_cec {
210			mux {
211				groups = "ao_cec";
212				function = "cec_ao";
213			};
214		};
215
216		ee_cec_pins: ee_cec {
217			mux {
218				groups = "ee_cec";
219				function = "cec_ao";
220			};
221		};
222	};
223};
224
225&apb {
226	mali: gpu@c0000 {
227		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
228		reg = <0x0 0xc0000 0x0 0x40000>;
229		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
230			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
231			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
232			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
233			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
234			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
235			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
236			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
237			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
238			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
239		interrupt-names = "gp", "gpmmu", "pp", "pmu",
240			"pp0", "ppmmu0", "pp1", "ppmmu1",
241			"pp2", "ppmmu2";
242		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
243		clock-names = "bus", "core";
244
245		/*
246		 * Mali clocking is provided by two identical clock paths
247		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
248		 * free mux to safely change frequency while running.
249		 */
250		assigned-clocks = <&clkc CLKID_GP0_PLL>,
251				  <&clkc CLKID_MALI_0_SEL>,
252				  <&clkc CLKID_MALI_0>,
253				  <&clkc CLKID_MALI>; /* Glitch free mux */
254		assigned-clock-parents = <0>, /* Do Nothing */
255					 <&clkc CLKID_GP0_PLL>,
256					 <0>, /* Do Nothing */
257					 <&clkc CLKID_MALI_0>;
258		assigned-clock-rates = <744000000>,
259				       <0>, /* Do Nothing */
260				       <744000000>,
261				       <0>; /* Do Nothing */
262	};
263};
264
265&cbus {
266	spifc: spi@8c80 {
267		compatible = "amlogic,meson-gxbb-spifc";
268		reg = <0x0 0x08c80 0x0 0x80>;
269		#address-cells = <1>;
270		#size-cells = <0>;
271		clocks = <&clkc CLKID_SPI>;
272		status = "disabled";
273	};
274};
275
276&cec_AO {
277	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
278	clock-names = "core";
279};
280
281&clkc_AO {
282	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
283};
284
285&ethmac {
286	clocks = <&clkc CLKID_ETH>,
287		 <&clkc CLKID_FCLK_DIV2>,
288		 <&clkc CLKID_MPLL2>;
289	clock-names = "stmmaceth", "clkin0", "clkin1";
290};
291
292&gpio_intc {
293	compatible = "amlogic,meson-gpio-intc",
294		     "amlogic,meson-gxbb-gpio-intc";
295	status = "okay";
296};
297
298&hdmi_tx {
299	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
300	resets = <&reset RESET_HDMITX_CAPB3>,
301		 <&reset RESET_HDMI_SYSTEM_RESET>,
302		 <&reset RESET_HDMI_TX>;
303	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
304	clocks = <&clkc CLKID_HDMI_PCLK>,
305		 <&clkc CLKID_CLK81>,
306		 <&clkc CLKID_GCLK_VENCI_INT0>;
307	clock-names = "isfr", "iahb", "venci";
308};
309
310&hiubus {
311	clkc: clock-controller@0 {
312		compatible = "amlogic,gxbb-clkc";
313		#clock-cells = <1>;
314		reg = <0x0 0x0 0x0 0x3db>;
315	};
316};
317
318&hwrng {
319	clocks = <&clkc CLKID_RNG0>;
320	clock-names = "core";
321};
322
323&i2c_A {
324	clocks = <&clkc CLKID_I2C>;
325};
326
327&i2c_AO {
328	clocks = <&clkc CLKID_AO_I2C>;
329};
330
331&i2c_B {
332	clocks = <&clkc CLKID_I2C>;
333};
334
335&i2c_C {
336	clocks = <&clkc CLKID_I2C>;
337};
338
339&periphs {
340	pinctrl_periphs: pinctrl@4b0 {
341		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
342		#address-cells = <2>;
343		#size-cells = <2>;
344		ranges;
345
346		gpio: bank@4b0 {
347			reg = <0x0 0x004b0 0x0 0x28>,
348			      <0x0 0x004e8 0x0 0x14>,
349			      <0x0 0x00520 0x0 0x14>,
350			      <0x0 0x00430 0x0 0x40>;
351			reg-names = "mux", "pull", "pull-enable", "gpio";
352			gpio-controller;
353			#gpio-cells = <2>;
354			gpio-ranges = <&pinctrl_periphs 0 0 119>;
355		};
356
357		emmc_pins: emmc {
358			mux {
359				groups = "emmc_nand_d07",
360				       "emmc_cmd",
361				       "emmc_clk";
362				function = "emmc";
363			};
364		};
365
366		emmc_ds_pins: emmc-ds {
367			mux {
368				groups = "emmc_ds";
369				function = "emmc";
370			};
371		};
372
373		emmc_clk_gate_pins: emmc_clk_gate {
374			mux {
375				groups = "BOOT_8";
376				function = "gpio_periphs";
377			};
378			cfg-pull-down {
379				pins = "BOOT_8";
380				bias-pull-down;
381			};
382		};
383
384		nor_pins: nor {
385			mux {
386				groups = "nor_d",
387				       "nor_q",
388				       "nor_c",
389				       "nor_cs";
390				function = "nor";
391			};
392		};
393
394		spi_pins: spi {
395			mux {
396				groups = "spi_miso",
397					"spi_mosi",
398					"spi_sclk";
399				function = "spi";
400			};
401		};
402
403		spi_ss0_pins: spi-ss0 {
404			mux {
405				groups = "spi_ss0";
406				function = "spi";
407			};
408		};
409
410		sdcard_pins: sdcard {
411			mux {
412				groups = "sdcard_d0",
413				       "sdcard_d1",
414				       "sdcard_d2",
415				       "sdcard_d3",
416				       "sdcard_cmd",
417				       "sdcard_clk";
418				function = "sdcard";
419			};
420		};
421
422		sdcard_clk_gate_pins: sdcard_clk_gate {
423			mux {
424				groups = "CARD_2";
425				function = "gpio_periphs";
426			};
427			cfg-pull-down {
428				pins = "CARD_2";
429				bias-pull-down;
430			};
431		};
432
433		sdio_pins: sdio {
434			mux {
435				groups = "sdio_d0",
436				       "sdio_d1",
437				       "sdio_d2",
438				       "sdio_d3",
439				       "sdio_cmd",
440				       "sdio_clk";
441				function = "sdio";
442			};
443		};
444
445		sdio_clk_gate_pins: sdio_clk_gate {
446			mux {
447				groups = "GPIOX_4";
448				function = "gpio_periphs";
449			};
450			cfg-pull-down {
451				pins = "GPIOX_4";
452				bias-pull-down;
453			};
454		};
455
456		sdio_irq_pins: sdio_irq {
457			mux {
458				groups = "sdio_irq";
459				function = "sdio";
460			};
461		};
462
463		uart_a_pins: uart_a {
464			mux {
465				groups = "uart_tx_a",
466				       "uart_rx_a";
467				function = "uart_a";
468			};
469		};
470
471		uart_a_cts_rts_pins: uart_a_cts_rts {
472			mux {
473				groups = "uart_cts_a",
474				       "uart_rts_a";
475				function = "uart_a";
476			};
477		};
478
479		uart_b_pins: uart_b {
480			mux {
481				groups = "uart_tx_b",
482				       "uart_rx_b";
483				function = "uart_b";
484			};
485		};
486
487		uart_b_cts_rts_pins: uart_b_cts_rts {
488			mux {
489				groups = "uart_cts_b",
490				       "uart_rts_b";
491				function = "uart_b";
492			};
493		};
494
495		uart_c_pins: uart_c {
496			mux {
497				groups = "uart_tx_c",
498				       "uart_rx_c";
499				function = "uart_c";
500			};
501		};
502
503		uart_c_cts_rts_pins: uart_c_cts_rts {
504			mux {
505				groups = "uart_cts_c",
506				       "uart_rts_c";
507				function = "uart_c";
508			};
509		};
510
511		i2c_a_pins: i2c_a {
512			mux {
513				groups = "i2c_sck_a",
514				       "i2c_sda_a";
515				function = "i2c_a";
516			};
517		};
518
519		i2c_b_pins: i2c_b {
520			mux {
521				groups = "i2c_sck_b",
522				       "i2c_sda_b";
523				function = "i2c_b";
524			};
525		};
526
527		i2c_c_pins: i2c_c {
528			mux {
529				groups = "i2c_sck_c",
530				       "i2c_sda_c";
531				function = "i2c_c";
532			};
533		};
534
535		eth_rgmii_pins: eth-rgmii {
536			mux {
537				groups = "eth_mdio",
538				       "eth_mdc",
539				       "eth_clk_rx_clk",
540				       "eth_rx_dv",
541				       "eth_rxd0",
542				       "eth_rxd1",
543				       "eth_rxd2",
544				       "eth_rxd3",
545				       "eth_rgmii_tx_clk",
546				       "eth_tx_en",
547				       "eth_txd0",
548				       "eth_txd1",
549				       "eth_txd2",
550				       "eth_txd3";
551				function = "eth";
552			};
553		};
554
555		eth_rmii_pins: eth-rmii {
556			mux {
557				groups = "eth_mdio",
558				       "eth_mdc",
559				       "eth_clk_rx_clk",
560				       "eth_rx_dv",
561				       "eth_rxd0",
562				       "eth_rxd1",
563				       "eth_tx_en",
564				       "eth_txd0",
565				       "eth_txd1";
566				function = "eth";
567			};
568		};
569
570		pwm_a_x_pins: pwm_a_x {
571			mux {
572				groups = "pwm_a_x";
573				function = "pwm_a_x";
574			};
575		};
576
577		pwm_a_y_pins: pwm_a_y {
578			mux {
579				groups = "pwm_a_y";
580				function = "pwm_a_y";
581			};
582		};
583
584		pwm_b_pins: pwm_b {
585			mux {
586				groups = "pwm_b";
587				function = "pwm_b";
588			};
589		};
590
591		pwm_d_pins: pwm_d {
592			mux {
593				groups = "pwm_d";
594				function = "pwm_d";
595			};
596		};
597
598		pwm_e_pins: pwm_e {
599			mux {
600				groups = "pwm_e";
601				function = "pwm_e";
602			};
603		};
604
605		pwm_f_x_pins: pwm_f_x {
606			mux {
607				groups = "pwm_f_x";
608				function = "pwm_f_x";
609			};
610		};
611
612		pwm_f_y_pins: pwm_f_y {
613			mux {
614				groups = "pwm_f_y";
615				function = "pwm_f_y";
616			};
617		};
618
619		hdmi_hpd_pins: hdmi_hpd {
620			mux {
621				groups = "hdmi_hpd";
622				function = "hdmi_hpd";
623			};
624		};
625
626		hdmi_i2c_pins: hdmi_i2c {
627			mux {
628				groups = "hdmi_sda", "hdmi_scl";
629				function = "hdmi_i2c";
630			};
631		};
632
633		i2sout_ch23_y_pins: i2sout_ch23_y {
634			mux {
635				groups = "i2sout_ch23_y";
636				function = "i2s_out";
637			};
638		};
639
640		i2sout_ch45_y_pins: i2sout_ch45_y {
641			mux {
642				groups = "i2sout_ch45_y";
643				function = "i2s_out";
644			};
645		};
646
647		i2sout_ch67_y_pins: i2sout_ch67_y {
648			mux {
649				groups = "i2sout_ch67_y";
650				function = "i2s_out";
651			};
652		};
653
654		spdif_out_y_pins: spdif_out_y {
655			mux {
656				groups = "spdif_out_y";
657				function = "spdif_out";
658			};
659		};
660	};
661};
662
663&pwrc_vpu {
664	resets = <&reset RESET_VIU>,
665		 <&reset RESET_VENC>,
666		 <&reset RESET_VCBUS>,
667		 <&reset RESET_BT656>,
668		 <&reset RESET_DVIN_RESET>,
669		 <&reset RESET_RDMA>,
670		 <&reset RESET_VENCI>,
671		 <&reset RESET_VENCP>,
672		 <&reset RESET_VDAC>,
673		 <&reset RESET_VDI6>,
674		 <&reset RESET_VENCL>,
675		 <&reset RESET_VID_LOCK>;
676	clocks = <&clkc CLKID_VPU>,
677	         <&clkc CLKID_VAPB>;
678	clock-names = "vpu", "vapb";
679	/*
680	 * VPU clocking is provided by two identical clock paths
681	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
682	 * free mux to safely change frequency while running.
683	 * Same for VAPB but with a final gate after the glitch free mux.
684	 */
685	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
686			  <&clkc CLKID_VPU_0>,
687			  <&clkc CLKID_VPU>, /* Glitch free mux */
688			  <&clkc CLKID_VAPB_0_SEL>,
689			  <&clkc CLKID_VAPB_0>,
690			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
691	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
692				 <0>, /* Do Nothing */
693				 <&clkc CLKID_VPU_0>,
694				 <&clkc CLKID_FCLK_DIV4>,
695				 <0>, /* Do Nothing */
696				 <&clkc CLKID_VAPB_0>;
697	assigned-clock-rates = <0>, /* Do Nothing */
698			       <666666666>,
699			       <0>, /* Do Nothing */
700			       <0>, /* Do Nothing */
701			       <250000000>,
702			       <0>; /* Do Nothing */
703};
704
705&saradc {
706	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
707	clocks = <&xtal>,
708		 <&clkc CLKID_SAR_ADC>,
709		 <&clkc CLKID_SAR_ADC_CLK>,
710		 <&clkc CLKID_SAR_ADC_SEL>;
711	clock-names = "clkin", "core", "adc_clk", "adc_sel";
712};
713
714&sd_emmc_a {
715	clocks = <&clkc CLKID_SD_EMMC_A>,
716		 <&clkc CLKID_SD_EMMC_A_CLK0>,
717		 <&clkc CLKID_FCLK_DIV2>;
718	clock-names = "core", "clkin0", "clkin1";
719};
720
721&sd_emmc_b {
722	clocks = <&clkc CLKID_SD_EMMC_B>,
723		 <&clkc CLKID_SD_EMMC_B_CLK0>,
724		 <&clkc CLKID_FCLK_DIV2>;
725	clock-names = "core", "clkin0", "clkin1";
726};
727
728&sd_emmc_c {
729	clocks = <&clkc CLKID_SD_EMMC_C>,
730		 <&clkc CLKID_SD_EMMC_C_CLK0>,
731		 <&clkc CLKID_FCLK_DIV2>;
732	clock-names = "core", "clkin0", "clkin1";
733};
734
735&spicc {
736	clocks = <&clkc CLKID_SPICC>;
737	clock-names = "core";
738	resets = <&reset RESET_PERIPHS_SPICC>;
739	num-cs = <1>;
740};
741
742&spifc {
743	clocks = <&clkc CLKID_SPI>;
744};
745
746&uart_A {
747	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
748	clock-names = "xtal", "pclk", "baud";
749};
750
751&uart_AO {
752	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
753	clock-names = "xtal", "pclk", "baud";
754};
755
756&uart_AO_B {
757	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
758	clock-names = "xtal", "pclk", "baud";
759};
760
761&uart_B {
762	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
763	clock-names = "xtal", "pclk", "baud";
764};
765
766&uart_C {
767	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
768	clock-names = "xtal", "pclk", "baud";
769};
770
771&vpu {
772	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
773	power-domains = <&pwrc_vpu>;
774};
775