xref: /openbmc/u-boot/arch/arm/dts/meson-gxbb.dtsi (revision b9553986) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Andreas Färber
4 */
5
6#include "meson-gx.dtsi"
7#include <dt-bindings/gpio/meson-gxbb-gpio.h>
8#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
9#include <dt-bindings/clock/gxbb-clkc.h>
10#include <dt-bindings/clock/gxbb-aoclkc.h>
11#include <dt-bindings/reset/gxbb-aoclkc.h>
12
13/ {
14	compatible = "amlogic,meson-gxbb";
15
16	soc {
17		usb0_phy: phy@c0000000 {
18			compatible = "amlogic,meson-gxbb-usb2-phy";
19			#phy-cells = <0>;
20			reg = <0x0 0xc0000000 0x0 0x20>;
21			resets = <&reset RESET_USB_OTG>;
22			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
23			clock-names = "usb_general", "usb";
24			status = "disabled";
25		};
26
27		usb1_phy: phy@c0000020 {
28			compatible = "amlogic,meson-gxbb-usb2-phy";
29			#phy-cells = <0>;
30			reg = <0x0 0xc0000020 0x0 0x20>;
31			resets = <&reset RESET_USB_OTG>;
32			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
33			clock-names = "usb_general", "usb";
34			status = "disabled";
35		};
36
37		usb0: usb@c9000000 {
38			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
39			reg = <0x0 0xc9000000 0x0 0x40000>;
40			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
41			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
42			clock-names = "otg";
43			phys = <&usb0_phy>;
44			phy-names = "usb2-phy";
45			dr_mode = "host";
46			status = "disabled";
47		};
48
49		usb1: usb@c9100000 {
50			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
51			reg = <0x0 0xc9100000 0x0 0x40000>;
52			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
53			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
54			clock-names = "otg";
55			phys = <&usb1_phy>;
56			phy-names = "usb2-phy";
57			dr_mode = "host";
58			status = "disabled";
59		};
60	};
61};
62
63&aobus {
64	pinctrl_aobus: pinctrl@14 {
65		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
66		#address-cells = <2>;
67		#size-cells = <2>;
68		ranges;
69
70		gpio_ao: bank@14 {
71			reg = <0x0 0x00014 0x0 0x8>,
72			      <0x0 0x0002c 0x0 0x4>,
73			      <0x0 0x00024 0x0 0x8>;
74			reg-names = "mux", "pull", "gpio";
75			gpio-controller;
76			#gpio-cells = <2>;
77			gpio-ranges = <&pinctrl_aobus 0 0 14>;
78		};
79
80		uart_ao_a_pins: uart_ao_a {
81			mux {
82				groups = "uart_tx_ao_a", "uart_rx_ao_a";
83				function = "uart_ao";
84			};
85		};
86
87		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
88			mux {
89				groups = "uart_cts_ao_a",
90				       "uart_rts_ao_a";
91				function = "uart_ao";
92			};
93		};
94
95		uart_ao_b_pins: uart_ao_b {
96			mux {
97				groups = "uart_tx_ao_b", "uart_rx_ao_b";
98				function = "uart_ao_b";
99			};
100		};
101
102		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
103			mux {
104				groups = "uart_cts_ao_b",
105				       "uart_rts_ao_b";
106				function = "uart_ao_b";
107			};
108		};
109
110		remote_input_ao_pins: remote_input_ao {
111			mux {
112				groups = "remote_input_ao";
113				function = "remote_input_ao";
114			};
115		};
116
117		i2c_ao_pins: i2c_ao {
118			mux {
119				groups = "i2c_sck_ao",
120				       "i2c_sda_ao";
121				function = "i2c_ao";
122			};
123		};
124
125		pwm_ao_a_3_pins: pwm_ao_a_3 {
126			mux {
127				groups = "pwm_ao_a_3";
128				function = "pwm_ao_a_3";
129			};
130		};
131
132		pwm_ao_a_6_pins: pwm_ao_a_6 {
133			mux {
134				groups = "pwm_ao_a_6";
135				function = "pwm_ao_a_6";
136			};
137		};
138
139		pwm_ao_a_12_pins: pwm_ao_a_12 {
140			mux {
141				groups = "pwm_ao_a_12";
142				function = "pwm_ao_a_12";
143			};
144		};
145
146		pwm_ao_b_pins: pwm_ao_b {
147			mux {
148				groups = "pwm_ao_b";
149				function = "pwm_ao_b";
150			};
151		};
152
153		i2s_am_clk_pins: i2s_am_clk {
154			mux {
155				groups = "i2s_am_clk";
156				function = "i2s_out_ao";
157			};
158		};
159
160		i2s_out_ao_clk_pins: i2s_out_ao_clk {
161			mux {
162				groups = "i2s_out_ao_clk";
163				function = "i2s_out_ao";
164			};
165		};
166
167		i2s_out_lr_clk_pins: i2s_out_lr_clk {
168			mux {
169				groups = "i2s_out_lr_clk";
170				function = "i2s_out_ao";
171			};
172		};
173
174		i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
175			mux {
176				groups = "i2s_out_ch01_ao";
177				function = "i2s_out_ao";
178			};
179		};
180
181		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
182			mux {
183				groups = "i2s_out_ch23_ao";
184				function = "i2s_out_ao";
185			};
186		};
187
188		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
189			mux {
190				groups = "i2s_out_ch45_ao";
191				function = "i2s_out_ao";
192			};
193		};
194
195		spdif_out_ao_6_pins: spdif_out_ao_6 {
196			mux {
197				groups = "spdif_out_ao_6";
198				function = "spdif_out_ao";
199			};
200		};
201
202		spdif_out_ao_13_pins: spdif_out_ao_13 {
203			mux {
204				groups = "spdif_out_ao_13";
205				function = "spdif_out_ao";
206			};
207		};
208
209		ao_cec_pins: ao_cec {
210			mux {
211				groups = "ao_cec";
212				function = "cec_ao";
213			};
214		};
215
216		ee_cec_pins: ee_cec {
217			mux {
218				groups = "ee_cec";
219				function = "cec_ao";
220			};
221		};
222	};
223};
224
225&apb {
226	mali: gpu@c0000 {
227		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
228		reg = <0x0 0xc0000 0x0 0x40000>;
229		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
230			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
231			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
232			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
233			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
234			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
235			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
236			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
237			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
238			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
239		interrupt-names = "gp", "gpmmu", "pp", "pmu",
240			"pp0", "ppmmu0", "pp1", "ppmmu1",
241			"pp2", "ppmmu2";
242		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
243		clock-names = "bus", "core";
244
245		/*
246		 * Mali clocking is provided by two identical clock paths
247		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
248		 * free mux to safely change frequency while running.
249		 */
250		assigned-clocks = <&clkc CLKID_GP0_PLL>,
251				  <&clkc CLKID_MALI_0_SEL>,
252				  <&clkc CLKID_MALI_0>,
253				  <&clkc CLKID_MALI>; /* Glitch free mux */
254		assigned-clock-parents = <0>, /* Do Nothing */
255					 <&clkc CLKID_GP0_PLL>,
256					 <0>, /* Do Nothing */
257					 <&clkc CLKID_MALI_0>;
258		assigned-clock-rates = <744000000>,
259				       <0>, /* Do Nothing */
260				       <744000000>,
261				       <0>; /* Do Nothing */
262	};
263};
264
265&cbus {
266	spifc: spi@8c80 {
267		compatible = "amlogic,meson-gxbb-spifc";
268		reg = <0x0 0x08c80 0x0 0x80>;
269		#address-cells = <1>;
270		#size-cells = <0>;
271		clocks = <&clkc CLKID_SPI>;
272		status = "disabled";
273	};
274};
275
276&cec_AO {
277	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
278	clock-names = "core";
279};
280
281&clkc_AO {
282	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
283};
284
285&ethmac {
286	clocks = <&clkc CLKID_ETH>,
287		 <&clkc CLKID_FCLK_DIV2>,
288		 <&clkc CLKID_MPLL2>;
289	clock-names = "stmmaceth", "clkin0", "clkin1";
290};
291
292&gpio_intc {
293	compatible = "amlogic,meson-gpio-intc",
294		     "amlogic,meson-gxbb-gpio-intc";
295	status = "okay";
296};
297
298&hdmi_tx {
299	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
300	resets = <&reset RESET_HDMITX_CAPB3>,
301		 <&reset RESET_HDMI_SYSTEM_RESET>,
302		 <&reset RESET_HDMI_TX>;
303	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
304	clocks = <&clkc CLKID_HDMI_PCLK>,
305		 <&clkc CLKID_CLK81>,
306		 <&clkc CLKID_GCLK_VENCI_INT0>;
307	clock-names = "isfr", "iahb", "venci";
308};
309
310&sysctrl {
311	clkc: clock-controller {
312		compatible = "amlogic,gxbb-clkc";
313		#clock-cells = <1>;
314	};
315};
316
317&hwrng {
318	clocks = <&clkc CLKID_RNG0>;
319	clock-names = "core";
320};
321
322&i2c_A {
323	clocks = <&clkc CLKID_I2C>;
324};
325
326&i2c_AO {
327	clocks = <&clkc CLKID_AO_I2C>;
328};
329
330&i2c_B {
331	clocks = <&clkc CLKID_I2C>;
332};
333
334&i2c_C {
335	clocks = <&clkc CLKID_I2C>;
336};
337
338&periphs {
339	pinctrl_periphs: pinctrl@4b0 {
340		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
341		#address-cells = <2>;
342		#size-cells = <2>;
343		ranges;
344
345		gpio: bank@4b0 {
346			reg = <0x0 0x004b0 0x0 0x28>,
347			      <0x0 0x004e8 0x0 0x14>,
348			      <0x0 0x00520 0x0 0x14>,
349			      <0x0 0x00430 0x0 0x40>;
350			reg-names = "mux", "pull", "pull-enable", "gpio";
351			gpio-controller;
352			#gpio-cells = <2>;
353			gpio-ranges = <&pinctrl_periphs 0 0 119>;
354		};
355
356		emmc_pins: emmc {
357			mux {
358				groups = "emmc_nand_d07",
359				       "emmc_cmd",
360				       "emmc_clk";
361				function = "emmc";
362			};
363		};
364
365		emmc_ds_pins: emmc-ds {
366			mux {
367				groups = "emmc_ds";
368				function = "emmc";
369			};
370		};
371
372		emmc_clk_gate_pins: emmc_clk_gate {
373			mux {
374				groups = "BOOT_8";
375				function = "gpio_periphs";
376			};
377			cfg-pull-down {
378				pins = "BOOT_8";
379				bias-pull-down;
380			};
381		};
382
383		nor_pins: nor {
384			mux {
385				groups = "nor_d",
386				       "nor_q",
387				       "nor_c",
388				       "nor_cs";
389				function = "nor";
390			};
391		};
392
393		spi_pins: spi-pins {
394			mux {
395				groups = "spi_miso",
396					"spi_mosi",
397					"spi_sclk";
398				function = "spi";
399			};
400		};
401
402		spi_ss0_pins: spi-ss0 {
403			mux {
404				groups = "spi_ss0";
405				function = "spi";
406			};
407		};
408
409		sdcard_pins: sdcard {
410			mux {
411				groups = "sdcard_d0",
412				       "sdcard_d1",
413				       "sdcard_d2",
414				       "sdcard_d3",
415				       "sdcard_cmd",
416				       "sdcard_clk";
417				function = "sdcard";
418			};
419		};
420
421		sdcard_clk_gate_pins: sdcard_clk_gate {
422			mux {
423				groups = "CARD_2";
424				function = "gpio_periphs";
425			};
426			cfg-pull-down {
427				pins = "CARD_2";
428				bias-pull-down;
429			};
430		};
431
432		sdio_pins: sdio {
433			mux {
434				groups = "sdio_d0",
435				       "sdio_d1",
436				       "sdio_d2",
437				       "sdio_d3",
438				       "sdio_cmd",
439				       "sdio_clk";
440				function = "sdio";
441			};
442		};
443
444		sdio_clk_gate_pins: sdio_clk_gate {
445			mux {
446				groups = "GPIOX_4";
447				function = "gpio_periphs";
448			};
449			cfg-pull-down {
450				pins = "GPIOX_4";
451				bias-pull-down;
452			};
453		};
454
455		sdio_irq_pins: sdio_irq {
456			mux {
457				groups = "sdio_irq";
458				function = "sdio";
459			};
460		};
461
462		uart_a_pins: uart_a {
463			mux {
464				groups = "uart_tx_a",
465				       "uart_rx_a";
466				function = "uart_a";
467			};
468		};
469
470		uart_a_cts_rts_pins: uart_a_cts_rts {
471			mux {
472				groups = "uart_cts_a",
473				       "uart_rts_a";
474				function = "uart_a";
475			};
476		};
477
478		uart_b_pins: uart_b {
479			mux {
480				groups = "uart_tx_b",
481				       "uart_rx_b";
482				function = "uart_b";
483			};
484		};
485
486		uart_b_cts_rts_pins: uart_b_cts_rts {
487			mux {
488				groups = "uart_cts_b",
489				       "uart_rts_b";
490				function = "uart_b";
491			};
492		};
493
494		uart_c_pins: uart_c {
495			mux {
496				groups = "uart_tx_c",
497				       "uart_rx_c";
498				function = "uart_c";
499			};
500		};
501
502		uart_c_cts_rts_pins: uart_c_cts_rts {
503			mux {
504				groups = "uart_cts_c",
505				       "uart_rts_c";
506				function = "uart_c";
507			};
508		};
509
510		i2c_a_pins: i2c_a {
511			mux {
512				groups = "i2c_sck_a",
513				       "i2c_sda_a";
514				function = "i2c_a";
515			};
516		};
517
518		i2c_b_pins: i2c_b {
519			mux {
520				groups = "i2c_sck_b",
521				       "i2c_sda_b";
522				function = "i2c_b";
523			};
524		};
525
526		i2c_c_pins: i2c_c {
527			mux {
528				groups = "i2c_sck_c",
529				       "i2c_sda_c";
530				function = "i2c_c";
531			};
532		};
533
534		eth_rgmii_pins: eth-rgmii {
535			mux {
536				groups = "eth_mdio",
537				       "eth_mdc",
538				       "eth_clk_rx_clk",
539				       "eth_rx_dv",
540				       "eth_rxd0",
541				       "eth_rxd1",
542				       "eth_rxd2",
543				       "eth_rxd3",
544				       "eth_rgmii_tx_clk",
545				       "eth_tx_en",
546				       "eth_txd0",
547				       "eth_txd1",
548				       "eth_txd2",
549				       "eth_txd3";
550				function = "eth";
551			};
552		};
553
554		eth_rmii_pins: eth-rmii {
555			mux {
556				groups = "eth_mdio",
557				       "eth_mdc",
558				       "eth_clk_rx_clk",
559				       "eth_rx_dv",
560				       "eth_rxd0",
561				       "eth_rxd1",
562				       "eth_tx_en",
563				       "eth_txd0",
564				       "eth_txd1";
565				function = "eth";
566			};
567		};
568
569		pwm_a_x_pins: pwm_a_x {
570			mux {
571				groups = "pwm_a_x";
572				function = "pwm_a_x";
573			};
574		};
575
576		pwm_a_y_pins: pwm_a_y {
577			mux {
578				groups = "pwm_a_y";
579				function = "pwm_a_y";
580			};
581		};
582
583		pwm_b_pins: pwm_b {
584			mux {
585				groups = "pwm_b";
586				function = "pwm_b";
587			};
588		};
589
590		pwm_d_pins: pwm_d {
591			mux {
592				groups = "pwm_d";
593				function = "pwm_d";
594			};
595		};
596
597		pwm_e_pins: pwm_e {
598			mux {
599				groups = "pwm_e";
600				function = "pwm_e";
601			};
602		};
603
604		pwm_f_x_pins: pwm_f_x {
605			mux {
606				groups = "pwm_f_x";
607				function = "pwm_f_x";
608			};
609		};
610
611		pwm_f_y_pins: pwm_f_y {
612			mux {
613				groups = "pwm_f_y";
614				function = "pwm_f_y";
615			};
616		};
617
618		hdmi_hpd_pins: hdmi_hpd {
619			mux {
620				groups = "hdmi_hpd";
621				function = "hdmi_hpd";
622			};
623		};
624
625		hdmi_i2c_pins: hdmi_i2c {
626			mux {
627				groups = "hdmi_sda", "hdmi_scl";
628				function = "hdmi_i2c";
629			};
630		};
631
632		i2sout_ch23_y_pins: i2sout_ch23_y {
633			mux {
634				groups = "i2sout_ch23_y";
635				function = "i2s_out";
636			};
637		};
638
639		i2sout_ch45_y_pins: i2sout_ch45_y {
640			mux {
641				groups = "i2sout_ch45_y";
642				function = "i2s_out";
643			};
644		};
645
646		i2sout_ch67_y_pins: i2sout_ch67_y {
647			mux {
648				groups = "i2sout_ch67_y";
649				function = "i2s_out";
650			};
651		};
652
653		spdif_out_y_pins: spdif_out_y {
654			mux {
655				groups = "spdif_out_y";
656				function = "spdif_out";
657			};
658		};
659	};
660};
661
662&pwrc_vpu {
663	resets = <&reset RESET_VIU>,
664		 <&reset RESET_VENC>,
665		 <&reset RESET_VCBUS>,
666		 <&reset RESET_BT656>,
667		 <&reset RESET_DVIN_RESET>,
668		 <&reset RESET_RDMA>,
669		 <&reset RESET_VENCI>,
670		 <&reset RESET_VENCP>,
671		 <&reset RESET_VDAC>,
672		 <&reset RESET_VDI6>,
673		 <&reset RESET_VENCL>,
674		 <&reset RESET_VID_LOCK>;
675	clocks = <&clkc CLKID_VPU>,
676	         <&clkc CLKID_VAPB>;
677	clock-names = "vpu", "vapb";
678	/*
679	 * VPU clocking is provided by two identical clock paths
680	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
681	 * free mux to safely change frequency while running.
682	 * Same for VAPB but with a final gate after the glitch free mux.
683	 */
684	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
685			  <&clkc CLKID_VPU_0>,
686			  <&clkc CLKID_VPU>, /* Glitch free mux */
687			  <&clkc CLKID_VAPB_0_SEL>,
688			  <&clkc CLKID_VAPB_0>,
689			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
690	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
691				 <0>, /* Do Nothing */
692				 <&clkc CLKID_VPU_0>,
693				 <&clkc CLKID_FCLK_DIV4>,
694				 <0>, /* Do Nothing */
695				 <&clkc CLKID_VAPB_0>;
696	assigned-clock-rates = <0>, /* Do Nothing */
697			       <666666666>,
698			       <0>, /* Do Nothing */
699			       <0>, /* Do Nothing */
700			       <250000000>,
701			       <0>; /* Do Nothing */
702};
703
704&saradc {
705	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
706	clocks = <&xtal>,
707		 <&clkc CLKID_SAR_ADC>,
708		 <&clkc CLKID_SAR_ADC_CLK>,
709		 <&clkc CLKID_SAR_ADC_SEL>;
710	clock-names = "clkin", "core", "adc_clk", "adc_sel";
711};
712
713&sd_emmc_a {
714	clocks = <&clkc CLKID_SD_EMMC_A>,
715		 <&clkc CLKID_SD_EMMC_A_CLK0>,
716		 <&clkc CLKID_FCLK_DIV2>;
717	clock-names = "core", "clkin0", "clkin1";
718	resets = <&reset RESET_SD_EMMC_A>;
719};
720
721&sd_emmc_b {
722	clocks = <&clkc CLKID_SD_EMMC_B>,
723		 <&clkc CLKID_SD_EMMC_B_CLK0>,
724		 <&clkc CLKID_FCLK_DIV2>;
725	clock-names = "core", "clkin0", "clkin1";
726	resets = <&reset RESET_SD_EMMC_B>;
727};
728
729&sd_emmc_c {
730	clocks = <&clkc CLKID_SD_EMMC_C>,
731		 <&clkc CLKID_SD_EMMC_C_CLK0>,
732		 <&clkc CLKID_FCLK_DIV2>;
733	clock-names = "core", "clkin0", "clkin1";
734	resets = <&reset RESET_SD_EMMC_C>;
735};
736
737&spicc {
738	clocks = <&clkc CLKID_SPICC>;
739	clock-names = "core";
740	resets = <&reset RESET_PERIPHS_SPICC>;
741	num-cs = <1>;
742};
743
744&spifc {
745	clocks = <&clkc CLKID_SPI>;
746};
747
748&uart_A {
749	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
750	clock-names = "xtal", "pclk", "baud";
751};
752
753&uart_AO {
754	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
755	clock-names = "xtal", "pclk", "baud";
756};
757
758&uart_AO_B {
759	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
760	clock-names = "xtal", "pclk", "baud";
761};
762
763&uart_B {
764	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
765	clock-names = "xtal", "pclk", "baud";
766};
767
768&uart_C {
769	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
770	clock-names = "xtal", "pclk", "baud";
771};
772
773&vpu {
774	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
775	power-domains = <&pwrc_vpu>;
776};
777