1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Freescale ls1021a SOC common device tree source 4 * 5 * Copyright 2013-2015 Freescale Semiconductor, Inc. 6 */ 7 8#include "skeleton.dtsi" 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "fsl,ls1021a"; 13 interrupt-parent = <&gic>; 14 15 aliases { 16 serial0 = &lpuart0; 17 serial1 = &lpuart1; 18 serial2 = &lpuart2; 19 serial3 = &lpuart3; 20 serial4 = &lpuart4; 21 serial5 = &lpuart5; 22 sysclk = &sysclk; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu@f00 { 30 compatible = "arm,cortex-a7"; 31 device_type = "cpu"; 32 reg = <0xf00>; 33 clocks = <&cluster1_clk>; 34 }; 35 36 cpu@f01 { 37 compatible = "arm,cortex-a7"; 38 device_type = "cpu"; 39 reg = <0xf01>; 40 clocks = <&cluster1_clk>; 41 }; 42 }; 43 44 timer { 45 compatible = "arm,armv7-timer"; 46 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 47 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 48 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 50 }; 51 52 pmu { 53 compatible = "arm,cortex-a7-pmu"; 54 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 56 }; 57 58 soc { 59 compatible = "simple-bus"; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 device_type = "soc"; 63 interrupt-parent = <&gic>; 64 ranges; 65 66 gic: interrupt-controller@1400000 { 67 compatible = "arm,cortex-a7-gic"; 68 #interrupt-cells = <3>; 69 interrupt-controller; 70 reg = <0x1401000 0x1000>, 71 <0x1402000 0x1000>, 72 <0x1404000 0x2000>, 73 <0x1406000 0x2000>; 74 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 75 76 }; 77 78 ifc: ifc@1530000 { 79 compatible = "fsl,ifc", "simple-bus"; 80 reg = <0x1530000 0x10000>; 81 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 82 }; 83 84 dcfg: dcfg@1ee0000 { 85 compatible = "fsl,ls1021a-dcfg", "syscon"; 86 reg = <0x1ee0000 0x10000>; 87 big-endian; 88 }; 89 90 esdhc: esdhc@1560000 { 91 compatible = "fsl,esdhc"; 92 reg = <0x1560000 0x10000>; 93 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 94 clock-frequency = <0>; 95 voltage-ranges = <1800 1800 3300 3300>; 96 sdhci,auto-cmd12; 97 big-endian; 98 bus-width = <4>; 99 }; 100 101 scfg: scfg@1570000 { 102 compatible = "fsl,ls1021a-scfg", "syscon"; 103 reg = <0x1570000 0x10000>; 104 big-endian; 105 }; 106 107 clockgen: clocking@1ee1000 { 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges = <0x0 0x1ee1000 0x10000>; 111 112 sysclk: sysclk { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-output-names = "sysclk"; 116 }; 117 118 cga_pll1: pll@800 { 119 compatible = "fsl,qoriq-core-pll-2.0"; 120 #clock-cells = <1>; 121 reg = <0x800 0x10>; 122 clocks = <&sysclk>; 123 clock-output-names = "cga-pll1", "cga-pll1-div2", 124 "cga-pll1-div4"; 125 }; 126 127 platform_clk: pll@c00 { 128 compatible = "fsl,qoriq-core-pll-2.0"; 129 #clock-cells = <1>; 130 reg = <0xc00 0x10>; 131 clocks = <&sysclk>; 132 clock-output-names = "platform-clk", "platform-clk-div2"; 133 }; 134 135 cluster1_clk: clk0c0@0 { 136 compatible = "fsl,qoriq-core-mux-2.0"; 137 #clock-cells = <0>; 138 reg = <0x0 0x10>; 139 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; 140 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; 141 clock-output-names = "cluster1-clk"; 142 }; 143 }; 144 145 dspi0: dspi@2100000 { 146 compatible = "fsl,vf610-dspi"; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 reg = <0x2100000 0x10000>; 150 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 151 clock-names = "dspi"; 152 clocks = <&platform_clk 1>; 153 num-cs = <6>; 154 big-endian; 155 status = "disabled"; 156 }; 157 158 dspi1: dspi@2110000 { 159 compatible = "fsl,vf610-dspi"; 160 #address-cells = <1>; 161 #size-cells = <0>; 162 reg = <0x2110000 0x10000>; 163 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 164 clock-names = "dspi"; 165 clocks = <&platform_clk 1>; 166 num-cs = <6>; 167 big-endian; 168 status = "disabled"; 169 }; 170 171 qspi: quadspi@1550000 { 172 compatible = "fsl,vf610-qspi"; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 reg = <0x1550000 0x10000>, 176 <0x40000000 0x4000000>; 177 reg-names = "QuadSPI", "QuadSPI-memory"; 178 num-cs = <2>; 179 big-endian; 180 status = "disabled"; 181 }; 182 183 i2c0: i2c@2180000 { 184 compatible = "fsl,vf610-i2c"; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 reg = <0x2180000 0x10000>; 188 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 189 clock-names = "i2c"; 190 clocks = <&platform_clk 1>; 191 status = "disabled"; 192 }; 193 194 i2c1: i2c@2190000 { 195 compatible = "fsl,vf610-i2c"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 reg = <0x2190000 0x10000>; 199 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 200 clock-names = "i2c"; 201 clocks = <&platform_clk 1>; 202 status = "disabled"; 203 }; 204 205 i2c2: i2c@21a0000 { 206 compatible = "fsl,vf610-i2c"; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 reg = <0x21a0000 0x10000>; 210 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 211 clock-names = "i2c"; 212 clocks = <&platform_clk 1>; 213 status = "disabled"; 214 }; 215 216 uart0: serial@21c0500 { 217 compatible = "fsl,16550-FIFO64", "ns16550a"; 218 reg = <0x21c0500 0x100>; 219 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 220 fifo-size = <15>; 221 status = "disabled"; 222 }; 223 224 uart1: serial@21c0600 { 225 compatible = "fsl,16550-FIFO64", "ns16550a"; 226 reg = <0x21c0600 0x100>; 227 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 228 fifo-size = <15>; 229 status = "disabled"; 230 }; 231 232 uart2: serial@21d0500 { 233 compatible = "fsl,16550-FIFO64", "ns16550a"; 234 reg = <0x21d0500 0x100>; 235 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 236 fifo-size = <15>; 237 status = "disabled"; 238 }; 239 240 uart3: serial@21d0600 { 241 compatible = "fsl,16550-FIFO64", "ns16550a"; 242 reg = <0x21d0600 0x100>; 243 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 244 fifo-size = <15>; 245 status = "disabled"; 246 }; 247 248 lpuart0: serial@2950000 { 249 compatible = "fsl,ls1021a-lpuart"; 250 reg = <0x2950000 0x1000>; 251 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&sysclk>; 253 clock-names = "ipg"; 254 status = "disabled"; 255 }; 256 257 lpuart1: serial@2960000 { 258 compatible = "fsl,ls1021a-lpuart"; 259 reg = <0x2960000 0x1000>; 260 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&platform_clk 1>; 262 clock-names = "ipg"; 263 status = "disabled"; 264 }; 265 266 lpuart2: serial@2970000 { 267 compatible = "fsl,ls1021a-lpuart"; 268 reg = <0x2970000 0x1000>; 269 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&platform_clk 1>; 271 clock-names = "ipg"; 272 status = "disabled"; 273 }; 274 275 lpuart3: serial@2980000 { 276 compatible = "fsl,ls1021a-lpuart"; 277 reg = <0x2980000 0x1000>; 278 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&platform_clk 1>; 280 clock-names = "ipg"; 281 status = "disabled"; 282 }; 283 284 lpuart4: serial@2990000 { 285 compatible = "fsl,ls1021a-lpuart"; 286 reg = <0x2990000 0x1000>; 287 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&platform_clk 1>; 289 clock-names = "ipg"; 290 status = "disabled"; 291 }; 292 293 lpuart5: serial@29a0000 { 294 compatible = "fsl,ls1021a-lpuart"; 295 reg = <0x29a0000 0x1000>; 296 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&platform_clk 1>; 298 clock-names = "ipg"; 299 status = "disabled"; 300 }; 301 302 wdog0: watchdog@2ad0000 { 303 compatible = "fsl,imx21-wdt"; 304 reg = <0x2ad0000 0x10000>; 305 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&platform_clk 1>; 307 clock-names = "wdog-en"; 308 big-endian; 309 }; 310 311 sai1: sai@2b50000 { 312 compatible = "fsl,vf610-sai"; 313 reg = <0x2b50000 0x10000>; 314 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&platform_clk 1>; 316 clock-names = "sai"; 317 dma-names = "tx", "rx"; 318 dmas = <&edma0 1 47>, 319 <&edma0 1 46>; 320 big-endian; 321 status = "disabled"; 322 }; 323 324 sai2: sai@2b60000 { 325 compatible = "fsl,vf610-sai"; 326 reg = <0x2b60000 0x10000>; 327 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&platform_clk 1>; 329 clock-names = "sai"; 330 dma-names = "tx", "rx"; 331 dmas = <&edma0 1 45>, 332 <&edma0 1 44>; 333 big-endian; 334 status = "disabled"; 335 }; 336 337 edma0: edma@2c00000 { 338 #dma-cells = <2>; 339 compatible = "fsl,vf610-edma"; 340 reg = <0x2c00000 0x10000>, 341 <0x2c10000 0x10000>, 342 <0x2c20000 0x10000>; 343 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 345 interrupt-names = "edma-tx", "edma-err"; 346 dma-channels = <32>; 347 big-endian; 348 clock-names = "dmamux0", "dmamux1"; 349 clocks = <&platform_clk 1>, 350 <&platform_clk 1>; 351 }; 352 353 mdio0: mdio@2d24000 { 354 compatible = "gianfar"; 355 device_type = "mdio"; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 reg = <0x2d24000 0x4000>; 359 }; 360 361 usb@8600000 { 362 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 363 reg = <0x8600000 0x1000>; 364 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 365 dr_mode = "host"; 366 phy_type = "ulpi"; 367 }; 368 369 usb3@3100000 { 370 compatible = "fsl,layerscape-dwc3"; 371 reg = <0x3100000 0x10000>; 372 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 373 dr_mode = "host"; 374 }; 375 376 pcie@3400000 { 377 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 378 reg = <0x03400000 0x20000 /* dbi registers */ 379 0x01570000 0x10000 /* pf controls registers */ 380 0x24000000 0x20000>; /* configuration space */ 381 reg-names = "dbi", "ctrl", "config"; 382 big-endian; 383 #address-cells = <3>; 384 #size-cells = <2>; 385 device_type = "pci"; 386 bus-range = <0x0 0xff>; 387 ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */ 388 0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */ 389 }; 390 391 pcie@3500000 { 392 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 393 reg = <0x03500000 0x10000 /* dbi registers */ 394 0x01570000 0x10000 /* pf controls registers */ 395 0x34000000 0x20000>; /* configuration space */ 396 reg-names = "dbi", "ctrl", "config"; 397 big-endian; 398 #address-cells = <3>; 399 #size-cells = <2>; 400 device_type = "pci"; 401 num-lanes = <2>; 402 bus-range = <0x0 0xff>; 403 ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */ 404 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */ 405 }; 406 407 sata: sata@3200000 { 408 compatible = "fsl,ls1021a-ahci"; 409 reg = <0x3200000 0x10000>; 410 interrupts = <0 101 4>; 411 status = "disabled"; 412 }; 413 }; 414}; 415