1/* 2 * Copyright 2013 Texas Instruments, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/gpio/gpio.h> 11 12#include "skeleton.dtsi" 13 14/ { 15 model = "Texas Instruments Keystone 2 SoC"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 interrupt-parent = <&gic>; 19 20 aliases { 21 serial0 = &uart0; 22 spi0 = &spi0; 23 spi1 = &spi1; 24 spi2 = &spi2; 25 }; 26 27 chosen { 28 stdout-path = &uart0; 29 }; 30 31 memory { 32 reg = <0x80000000 0x40000000>; 33 }; 34 35 gic: interrupt-controller { 36 compatible = "arm,cortex-a15-gic"; 37 #interrupt-cells = <3>; 38 interrupt-controller; 39 reg = <0x02561000 0x1000>, 40 <0x02562000 0x2000>, 41 <0x02564000 0x1000>, 42 <0x02566000 0x2000>; 43 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 44 IRQ_TYPE_LEVEL_HIGH)>; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 interrupts = 50 <GIC_PPI 13 51 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 14 53 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 54 <GIC_PPI 11 55 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 56 <GIC_PPI 10 57 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 58 }; 59 60 pmu { 61 compatible = "arm,cortex-a15-pmu"; 62 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>, 63 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 64 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>, 65 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 66 }; 67 68 soc { 69 #address-cells = <1>; 70 #size-cells = <1>; 71 compatible = "ti,keystone","simple-bus"; 72 interrupt-parent = <&gic>; 73 ranges; 74 75 pllctrl: pll-controller@02310000 { 76 compatible = "ti,keystone-pllctrl", "syscon"; 77 reg = <0x02310000 0x200>; 78 }; 79 80 devctrl: device-state-control@02620000 { 81 compatible = "ti,keystone-devctrl", "syscon"; 82 reg = <0x02620000 0x1000>; 83 }; 84 85 rstctrl: reset-controller { 86 compatible = "ti,keystone-reset"; 87 ti,syscon-pll = <&pllctrl 0xe4>; 88 ti,syscon-dev = <&devctrl 0x328>; 89 ti,wdt-list = <0>; 90 }; 91 92 /include/ "keystone-clocks.dtsi" 93 94 uart0: serial@02530c00 { 95 compatible = "ns16550a"; 96 current-speed = <115200>; 97 reg-shift = <2>; 98 reg-io-width = <4>; 99 reg = <0x02530c00 0x100>; 100 clocks = <&clkuart0>; 101 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 102 }; 103 104 uart1: serial@02531000 { 105 compatible = "ns16550a"; 106 current-speed = <115200>; 107 reg-shift = <2>; 108 reg-io-width = <4>; 109 reg = <0x02531000 0x100>; 110 clocks = <&clkuart1>; 111 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; 112 }; 113 114 i2c0: i2c@2530000 { 115 compatible = "ti,davinci-i2c"; 116 reg = <0x02530000 0x400>; 117 clock-frequency = <100000>; 118 clocks = <&clki2c>; 119 interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 }; 123 124 i2c1: i2c@2530400 { 125 compatible = "ti,davinci-i2c"; 126 reg = <0x02530400 0x400>; 127 clock-frequency = <100000>; 128 clocks = <&clki2c>; 129 interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 }; 133 134 i2c2: i2c@2530800 { 135 compatible = "ti,davinci-i2c"; 136 reg = <0x02530800 0x400>; 137 clock-frequency = <100000>; 138 clocks = <&clki2c>; 139 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 }; 143 144 spi0: spi@21000400 { 145 compatible = "ti,dm6441-spi"; 146 reg = <0x21000400 0x200>; 147 num-cs = <4>; 148 ti,davinci-spi-intr-line = <0>; 149 interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>; 150 clocks = <&clkspi>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 }; 154 155 spi1: spi@21000600 { 156 compatible = "ti,dm6441-spi"; 157 reg = <0x21000600 0x200>; 158 num-cs = <4>; 159 ti,davinci-spi-intr-line = <0>; 160 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>; 161 clocks = <&clkspi>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 }; 165 166 spi2: spi@21000800 { 167 compatible = "ti,dm6441-spi"; 168 reg = <0x21000800 0x200>; 169 num-cs = <4>; 170 ti,davinci-spi-intr-line = <0>; 171 interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; 172 clocks = <&clkspi>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 }; 176 177 usb_phy: usb_phy@2620738 { 178 compatible = "ti,keystone-usbphy"; 179 #address-cells = <1>; 180 #size-cells = <1>; 181 reg = <0x2620738 24>; 182 status = "disabled"; 183 }; 184 185 usb: usb@2680000 { 186 compatible = "ti,keystone-dwc3"; 187 #address-cells = <1>; 188 #size-cells = <1>; 189 reg = <0x2680000 0x10000>; 190 clocks = <&clkusb>; 191 clock-names = "usb"; 192 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; 193 ranges; 194 dma-coherent; 195 dma-ranges; 196 status = "disabled"; 197 198 dwc3@2690000 { 199 compatible = "synopsys,dwc3"; 200 reg = <0x2690000 0x70000>; 201 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; 202 usb-phy = <&usb_phy>, <&usb_phy>; 203 }; 204 }; 205 206 wdt: wdt@022f0080 { 207 compatible = "ti,keystone-wdt","ti,davinci-wdt"; 208 reg = <0x022f0080 0x80>; 209 clocks = <&clkwdtimer0>; 210 }; 211 212 clock_event: timer@22f0000 { 213 compatible = "ti,keystone-timer"; 214 reg = <0x022f0000 0x80>; 215 interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>; 216 clocks = <&clktimer15>; 217 }; 218 219 gpio0: gpio@260bf00 { 220 compatible = "ti,keystone-gpio"; 221 reg = <0x0260bf00 0x100>; 222 gpio-controller; 223 #gpio-cells = <2>; 224 /* HW Interrupts mapped to GPIO pins */ 225 interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, 226 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, 227 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 228 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, 229 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, 230 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 231 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 232 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 233 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 234 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 235 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 236 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 237 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 238 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 239 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 240 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 241 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 242 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 243 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 244 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 245 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, 246 <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 247 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, 248 <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>, 249 <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>, 250 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 251 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, 252 <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>, 253 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, 254 <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 255 <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>, 256 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 257 clocks = <&clkgpio>; 258 clock-names = "gpio"; 259 ti,ngpio = <32>; 260 ti,davinci-gpio-unbanked = <32>; 261 }; 262 263 aemif: aemif@21000A00 { 264 compatible = "ti,keystone-aemif", "ti,davinci-aemif"; 265 #address-cells = <2>; 266 #size-cells = <1>; 267 clocks = <&clkaemif>; 268 clock-names = "aemif"; 269 clock-ranges; 270 271 reg = <0x21000A00 0x00000100>; 272 ranges = <0 0 0x30000000 0x10000000 273 1 0 0x21000A00 0x00000100>; 274 }; 275 276 kirq0: keystone_irq@26202a0 { 277 compatible = "ti,keystone-irq"; 278 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 279 interrupt-controller; 280 #interrupt-cells = <1>; 281 ti,syscon-dev = <&devctrl 0x2a0>; 282 }; 283 284 pcie0: pcie@21800000 { 285 compatible = "ti,keystone-pcie", "snps,dw-pcie"; 286 clocks = <&clkpcie>; 287 clock-names = "pcie"; 288 #address-cells = <3>; 289 #size-cells = <2>; 290 reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; 291 ranges = <0x81000000 0 0 0x23250000 0 0x4000 292 0x82000000 0 0x50000000 0x50000000 0 0x10000000>; 293 294 status = "disabled"; 295 device_type = "pci"; 296 num-lanes = <2>; 297 298 #interrupt-cells = <1>; 299 interrupt-map-mask = <0 0 0 7>; 300 interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ 301 <0 0 0 2 &pcie_intc0 1>, /* INT B */ 302 <0 0 0 3 &pcie_intc0 2>, /* INT C */ 303 <0 0 0 4 &pcie_intc0 3>; /* INT D */ 304 305 pcie_msi_intc0: msi-interrupt-controller { 306 interrupt-controller; 307 #interrupt-cells = <1>; 308 interrupt-parent = <&gic>; 309 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 310 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 311 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 312 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 313 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 316 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; 317 }; 318 319 pcie_intc0: legacy-interrupt-controller { 320 interrupt-controller; 321 #interrupt-cells = <1>; 322 interrupt-parent = <&gic>; 323 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 325 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 326 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; 327 }; 328 }; 329 }; 330}; 331