1*f0a3f349SLokesh Vutla/* 2*f0a3f349SLokesh Vutla * Copyright 2014 Texas Instruments, Inc. 3*f0a3f349SLokesh Vutla * 4*f0a3f349SLokesh Vutla * Keystone 2 Edison SoC specific device tree 5*f0a3f349SLokesh Vutla * 6*f0a3f349SLokesh Vutla * This program is free software; you can redistribute it and/or modify 7*f0a3f349SLokesh Vutla * it under the terms of the GNU General Public License version 2 as 8*f0a3f349SLokesh Vutla * published by the Free Software Foundation. 9*f0a3f349SLokesh Vutla */ 10*f0a3f349SLokesh Vutla 11*f0a3f349SLokesh Vutlaclocks { 12*f0a3f349SLokesh Vutla mainpllclk: mainpllclk@2310110 { 13*f0a3f349SLokesh Vutla #clock-cells = <0>; 14*f0a3f349SLokesh Vutla compatible = "ti,keystone,main-pll-clock"; 15*f0a3f349SLokesh Vutla clocks = <&refclksys>; 16*f0a3f349SLokesh Vutla reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; 17*f0a3f349SLokesh Vutla reg-names = "control", "multiplier", "post-divider"; 18*f0a3f349SLokesh Vutla }; 19*f0a3f349SLokesh Vutla 20*f0a3f349SLokesh Vutla papllclk: papllclk@2620358 { 21*f0a3f349SLokesh Vutla #clock-cells = <0>; 22*f0a3f349SLokesh Vutla compatible = "ti,keystone,pll-clock"; 23*f0a3f349SLokesh Vutla clocks = <&refclkpass>; 24*f0a3f349SLokesh Vutla clock-output-names = "papllclk"; 25*f0a3f349SLokesh Vutla reg = <0x02620358 4>; 26*f0a3f349SLokesh Vutla reg-names = "control"; 27*f0a3f349SLokesh Vutla }; 28*f0a3f349SLokesh Vutla 29*f0a3f349SLokesh Vutla ddr3apllclk: ddr3apllclk@2620360 { 30*f0a3f349SLokesh Vutla #clock-cells = <0>; 31*f0a3f349SLokesh Vutla compatible = "ti,keystone,pll-clock"; 32*f0a3f349SLokesh Vutla clocks = <&refclkddr3a>; 33*f0a3f349SLokesh Vutla clock-output-names = "ddr-3a-pll-clk"; 34*f0a3f349SLokesh Vutla reg = <0x02620360 4>; 35*f0a3f349SLokesh Vutla reg-names = "control"; 36*f0a3f349SLokesh Vutla }; 37*f0a3f349SLokesh Vutla 38*f0a3f349SLokesh Vutla clkusb1: clkusb1 { 39*f0a3f349SLokesh Vutla #clock-cells = <0>; 40*f0a3f349SLokesh Vutla compatible = "ti,keystone,psc-clock"; 41*f0a3f349SLokesh Vutla clocks = <&chipclk16>; 42*f0a3f349SLokesh Vutla clock-output-names = "usb1"; 43*f0a3f349SLokesh Vutla reg = <0x02350004 0xb00>, <0x02350000 0x400>; 44*f0a3f349SLokesh Vutla reg-names = "control", "domain"; 45*f0a3f349SLokesh Vutla domain-id = <0>; 46*f0a3f349SLokesh Vutla }; 47*f0a3f349SLokesh Vutla 48*f0a3f349SLokesh Vutla clkhyperlink0: clkhyperlink0 { 49*f0a3f349SLokesh Vutla #clock-cells = <0>; 50*f0a3f349SLokesh Vutla compatible = "ti,keystone,psc-clock"; 51*f0a3f349SLokesh Vutla clocks = <&chipclk12>; 52*f0a3f349SLokesh Vutla clock-output-names = "hyperlink-0"; 53*f0a3f349SLokesh Vutla reg = <0x02350030 0xb00>, <0x02350014 0x400>; 54*f0a3f349SLokesh Vutla reg-names = "control", "domain"; 55*f0a3f349SLokesh Vutla domain-id = <5>; 56*f0a3f349SLokesh Vutla }; 57*f0a3f349SLokesh Vutla 58*f0a3f349SLokesh Vutla clkpcie1: clkpcie1 { 59*f0a3f349SLokesh Vutla #clock-cells = <0>; 60*f0a3f349SLokesh Vutla compatible = "ti,keystone,psc-clock"; 61*f0a3f349SLokesh Vutla clocks = <&chipclk12>; 62*f0a3f349SLokesh Vutla clock-output-names = "pcie1"; 63*f0a3f349SLokesh Vutla reg = <0x0235006c 0xb00>, <0x02350048 0x400>; 64*f0a3f349SLokesh Vutla reg-names = "control", "domain"; 65*f0a3f349SLokesh Vutla domain-id = <18>; 66*f0a3f349SLokesh Vutla }; 67*f0a3f349SLokesh Vutla 68*f0a3f349SLokesh Vutla clkxge: clkxge { 69*f0a3f349SLokesh Vutla #clock-cells = <0>; 70*f0a3f349SLokesh Vutla compatible = "ti,keystone,psc-clock"; 71*f0a3f349SLokesh Vutla clocks = <&chipclk13>; 72*f0a3f349SLokesh Vutla clock-output-names = "xge"; 73*f0a3f349SLokesh Vutla reg = <0x023500c8 0xb00>, <0x02350074 0x400>; 74*f0a3f349SLokesh Vutla reg-names = "control", "domain"; 75*f0a3f349SLokesh Vutla domain-id = <29>; 76*f0a3f349SLokesh Vutla }; 77*f0a3f349SLokesh Vutla}; 78