1*00b34e99SLokesh Vutla// SPDX-License-Identifier: GPL-2.0+ 2*00b34e99SLokesh Vutla/* 3*00b34e99SLokesh Vutla * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 4*00b34e99SLokesh Vutla */ 5*00b34e99SLokesh Vutla 6*00b34e99SLokesh Vutla/ { 7*00b34e99SLokesh Vutla memorycontroller: memorycontroller@0298e000 { 8*00b34e99SLokesh Vutla compatible = "ti,am654-ddrss"; 9*00b34e99SLokesh Vutla reg = <0x0 0x0298e000 0x0 0x200>, 10*00b34e99SLokesh Vutla <0x0 0x02980000 0x0 0x4000>, 11*00b34e99SLokesh Vutla <0x0 0x02988000 0x0 0x2000>; 12*00b34e99SLokesh Vutla reg-names = "ss", "ctl", "phy"; 13*00b34e99SLokesh Vutla clocks = <&k3_clks 20 0>; 14*00b34e99SLokesh Vutla power-domains = <&k3_pds 20>, 15*00b34e99SLokesh Vutla <&k3_pds 244>; 16*00b34e99SLokesh Vutla assigned-clocks = <&k3_clks 20 1>; 17*00b34e99SLokesh Vutla assigned-clock-rates = <DDR_PLL_FREQUENCY>; 18*00b34e99SLokesh Vutla u-boot,dm-spl; 19*00b34e99SLokesh Vutla 20*00b34e99SLokesh Vutla ti,ctl-reg = < 21*00b34e99SLokesh Vutla DDRCTL_DFIMISC 22*00b34e99SLokesh Vutla DDRCTL_DFITMG0 23*00b34e99SLokesh Vutla DDRCTL_DFITMG1 24*00b34e99SLokesh Vutla DDRCTL_DFITMG2 25*00b34e99SLokesh Vutla DDRCTL_INIT0 26*00b34e99SLokesh Vutla DDRCTL_INIT1 27*00b34e99SLokesh Vutla DDRCTL_INIT3 28*00b34e99SLokesh Vutla DDRCTL_INIT4 29*00b34e99SLokesh Vutla DDRCTL_INIT5 30*00b34e99SLokesh Vutla DDRCTL_INIT6 31*00b34e99SLokesh Vutla DDRCTL_INIT7 32*00b34e99SLokesh Vutla DDRCTL_MSTR 33*00b34e99SLokesh Vutla DDRCTL_ODTCFG 34*00b34e99SLokesh Vutla DDRCTL_ODTMAP 35*00b34e99SLokesh Vutla DDRCTL_RANKCTL 36*00b34e99SLokesh Vutla DDRCTL_RFSHCTL0 37*00b34e99SLokesh Vutla DDRCTL_RFSHTMG 38*00b34e99SLokesh Vutla DDRCTL_ZQCTL0 39*00b34e99SLokesh Vutla DDRCTL_ZQCTL1 40*00b34e99SLokesh Vutla >; 41*00b34e99SLokesh Vutla 42*00b34e99SLokesh Vutla ti,ctl-crc = < 43*00b34e99SLokesh Vutla DDRCTL_CRCPARCTL0 44*00b34e99SLokesh Vutla DDRCTL_CRCPARCTL1 45*00b34e99SLokesh Vutla DDRCTL_CRCPARCTL2 46*00b34e99SLokesh Vutla >; 47*00b34e99SLokesh Vutla 48*00b34e99SLokesh Vutla ti,ctl-ecc = < 49*00b34e99SLokesh Vutla DDRCTL_ECCCFG0 50*00b34e99SLokesh Vutla >; 51*00b34e99SLokesh Vutla 52*00b34e99SLokesh Vutla ti,ctl-map = < 53*00b34e99SLokesh Vutla DDRCTL_ADDRMAP0 54*00b34e99SLokesh Vutla DDRCTL_ADDRMAP1 55*00b34e99SLokesh Vutla DDRCTL_ADDRMAP2 56*00b34e99SLokesh Vutla DDRCTL_ADDRMAP3 57*00b34e99SLokesh Vutla DDRCTL_ADDRMAP4 58*00b34e99SLokesh Vutla DDRCTL_ADDRMAP5 59*00b34e99SLokesh Vutla DDRCTL_ADDRMAP6 60*00b34e99SLokesh Vutla DDRCTL_ADDRMAP7 61*00b34e99SLokesh Vutla DDRCTL_ADDRMAP8 62*00b34e99SLokesh Vutla DDRCTL_ADDRMAP9 63*00b34e99SLokesh Vutla DDRCTL_ADDRMAP10 64*00b34e99SLokesh Vutla DDRCTL_ADDRMAP11 65*00b34e99SLokesh Vutla DDRCTL_DQMAP0 66*00b34e99SLokesh Vutla DDRCTL_DQMAP1 67*00b34e99SLokesh Vutla DDRCTL_DQMAP4 68*00b34e99SLokesh Vutla DDRCTL_DQMAP5 69*00b34e99SLokesh Vutla >; 70*00b34e99SLokesh Vutla 71*00b34e99SLokesh Vutla ti,ctl-pwr = < 72*00b34e99SLokesh Vutla DDRCTL_PWRCTL 73*00b34e99SLokesh Vutla >; 74*00b34e99SLokesh Vutla 75*00b34e99SLokesh Vutla ti,ctl-timing = < 76*00b34e99SLokesh Vutla DDRCTL_DRAMTMG0 77*00b34e99SLokesh Vutla DDRCTL_DRAMTMG1 78*00b34e99SLokesh Vutla DDRCTL_DRAMTMG2 79*00b34e99SLokesh Vutla DDRCTL_DRAMTMG3 80*00b34e99SLokesh Vutla DDRCTL_DRAMTMG4 81*00b34e99SLokesh Vutla DDRCTL_DRAMTMG5 82*00b34e99SLokesh Vutla DDRCTL_DRAMTMG6 83*00b34e99SLokesh Vutla DDRCTL_DRAMTMG7 84*00b34e99SLokesh Vutla DDRCTL_DRAMTMG8 85*00b34e99SLokesh Vutla DDRCTL_DRAMTMG9 86*00b34e99SLokesh Vutla DDRCTL_DRAMTMG11 87*00b34e99SLokesh Vutla DDRCTL_DRAMTMG12 88*00b34e99SLokesh Vutla DDRCTL_DRAMTMG13 89*00b34e99SLokesh Vutla DDRCTL_DRAMTMG14 90*00b34e99SLokesh Vutla DDRCTL_DRAMTMG15 91*00b34e99SLokesh Vutla DDRCTL_DRAMTMG17 92*00b34e99SLokesh Vutla >; 93*00b34e99SLokesh Vutla 94*00b34e99SLokesh Vutla ti,phy-cfg = < 95*00b34e99SLokesh Vutla DDRPHY_DCR 96*00b34e99SLokesh Vutla DDRPHY_DSGCR 97*00b34e99SLokesh Vutla DDRPHY_DX0GCR0 98*00b34e99SLokesh Vutla DDRPHY_DX0GCR1 99*00b34e99SLokesh Vutla DDRPHY_DX0GCR2 100*00b34e99SLokesh Vutla DDRPHY_DX0GCR3 101*00b34e99SLokesh Vutla DDRPHY_DX0GCR4 102*00b34e99SLokesh Vutla DDRPHY_DX0GCR5 103*00b34e99SLokesh Vutla DDRPHY_DX0GTR0 104*00b34e99SLokesh Vutla DDRPHY_DX1GCR0 105*00b34e99SLokesh Vutla DDRPHY_DX1GCR1 106*00b34e99SLokesh Vutla DDRPHY_DX1GCR2 107*00b34e99SLokesh Vutla DDRPHY_DX1GCR3 108*00b34e99SLokesh Vutla DDRPHY_DX1GCR4 109*00b34e99SLokesh Vutla DDRPHY_DX1GCR5 110*00b34e99SLokesh Vutla DDRPHY_DX1GTR0 111*00b34e99SLokesh Vutla DDRPHY_DX2GCR0 112*00b34e99SLokesh Vutla DDRPHY_DX2GCR1 113*00b34e99SLokesh Vutla DDRPHY_DX2GCR2 114*00b34e99SLokesh Vutla DDRPHY_DX2GCR3 115*00b34e99SLokesh Vutla DDRPHY_DX2GCR4 116*00b34e99SLokesh Vutla DDRPHY_DX2GCR5 117*00b34e99SLokesh Vutla DDRPHY_DX2GTR0 118*00b34e99SLokesh Vutla DDRPHY_DX3GCR0 119*00b34e99SLokesh Vutla DDRPHY_DX3GCR1 120*00b34e99SLokesh Vutla DDRPHY_DX3GCR2 121*00b34e99SLokesh Vutla DDRPHY_DX3GCR3 122*00b34e99SLokesh Vutla DDRPHY_DX3GCR4 123*00b34e99SLokesh Vutla DDRPHY_DX3GCR5 124*00b34e99SLokesh Vutla DDRPHY_DX3GTR0 125*00b34e99SLokesh Vutla DDRPHY_DX4GCR0 126*00b34e99SLokesh Vutla DDRPHY_DX4GCR1 127*00b34e99SLokesh Vutla DDRPHY_DX4GCR2 128*00b34e99SLokesh Vutla DDRPHY_DX4GCR3 129*00b34e99SLokesh Vutla DDRPHY_DX4GCR4 130*00b34e99SLokesh Vutla DDRPHY_DX4GCR5 131*00b34e99SLokesh Vutla DDRPHY_DX4GTR0 132*00b34e99SLokesh Vutla DDRPHY_DX8SL0DXCTL2 133*00b34e99SLokesh Vutla DDRPHY_DX8SL0IOCR 134*00b34e99SLokesh Vutla DDRPHY_DX8SL0PLLCR0 135*00b34e99SLokesh Vutla DDRPHY_DX8SL1DXCTL2 136*00b34e99SLokesh Vutla DDRPHY_DX8SL1IOCR 137*00b34e99SLokesh Vutla DDRPHY_DX8SL1PLLCR0 138*00b34e99SLokesh Vutla DDRPHY_DX8SL2DXCTL2 139*00b34e99SLokesh Vutla DDRPHY_DX8SL2IOCR 140*00b34e99SLokesh Vutla DDRPHY_DX8SL2PLLCR0 141*00b34e99SLokesh Vutla DDRPHY_DXCCR 142*00b34e99SLokesh Vutla DDRPHY_ODTCR 143*00b34e99SLokesh Vutla DDRPHY_PGCR0 144*00b34e99SLokesh Vutla DDRPHY_PGCR1 145*00b34e99SLokesh Vutla DDRPHY_PGCR2 146*00b34e99SLokesh Vutla DDRPHY_PGCR3 147*00b34e99SLokesh Vutla DDRPHY_PGCR5 148*00b34e99SLokesh Vutla DDRPHY_PGCR6 149*00b34e99SLokesh Vutla >; 150*00b34e99SLokesh Vutla 151*00b34e99SLokesh Vutla ti,phy-ctl = < 152*00b34e99SLokesh Vutla DDRPHY_DTCR0 153*00b34e99SLokesh Vutla DDRPHY_DTCR1 154*00b34e99SLokesh Vutla DDRPHY_MR0 155*00b34e99SLokesh Vutla DDRPHY_MR1 156*00b34e99SLokesh Vutla DDRPHY_MR2 157*00b34e99SLokesh Vutla DDRPHY_MR3 158*00b34e99SLokesh Vutla DDRPHY_MR4 159*00b34e99SLokesh Vutla DDRPHY_MR5 160*00b34e99SLokesh Vutla DDRPHY_MR6 161*00b34e99SLokesh Vutla DDRPHY_MR11 162*00b34e99SLokesh Vutla DDRPHY_MR12 163*00b34e99SLokesh Vutla DDRPHY_MR13 164*00b34e99SLokesh Vutla DDRPHY_MR14 165*00b34e99SLokesh Vutla DDRPHY_MR22 166*00b34e99SLokesh Vutla DDRPHY_PLLCR0 167*00b34e99SLokesh Vutla DDRPHY_VTCR0 168*00b34e99SLokesh Vutla >; 169*00b34e99SLokesh Vutla 170*00b34e99SLokesh Vutla ti,phy-ioctl = < 171*00b34e99SLokesh Vutla DDRPHY_ACIOCR5 172*00b34e99SLokesh Vutla DDRPHY_IOVCR0 173*00b34e99SLokesh Vutla >; 174*00b34e99SLokesh Vutla 175*00b34e99SLokesh Vutla ti,phy-timing = < 176*00b34e99SLokesh Vutla DDRPHY_DTPR0 177*00b34e99SLokesh Vutla DDRPHY_DTPR1 178*00b34e99SLokesh Vutla DDRPHY_DTPR2 179*00b34e99SLokesh Vutla DDRPHY_DTPR3 180*00b34e99SLokesh Vutla DDRPHY_DTPR4 181*00b34e99SLokesh Vutla DDRPHY_DTPR5 182*00b34e99SLokesh Vutla DDRPHY_DTPR6 183*00b34e99SLokesh Vutla DDRPHY_PTR2 184*00b34e99SLokesh Vutla DDRPHY_PTR3 185*00b34e99SLokesh Vutla DDRPHY_PTR4 186*00b34e99SLokesh Vutla DDRPHY_PTR5 187*00b34e99SLokesh Vutla DDRPHY_PTR6 188*00b34e99SLokesh Vutla >; 189*00b34e99SLokesh Vutla 190*00b34e99SLokesh Vutla ti,phy-zq = < 191*00b34e99SLokesh Vutla DDRPHY_ZQ0PR0 192*00b34e99SLokesh Vutla DDRPHY_ZQ1PR0 193*00b34e99SLokesh Vutla DDRPHY_ZQCR 194*00b34e99SLokesh Vutla >; 195*00b34e99SLokesh Vutla }; 196*00b34e99SLokesh Vutla}; 197