121fbb558Sryan_chen /* SPDX-License-Identifier: GPL-2.0+ */
221fbb558Sryan_chen /*
321fbb558Sryan_chen  * Copyright (C) ASPEED Technology Inc.
421fbb558Sryan_chen  */
521fbb558Sryan_chen 
6*c8ffe8c6Sryan_chen #ifndef _MACH_ASPEED_AST2600_RESET_H_
7*c8ffe8c6Sryan_chen #define _MACH_ASPEED_AST2600_RESET_H_
821fbb558Sryan_chen 
921fbb558Sryan_chen #define ASPEED_RESET_FSI		(59)
1021fbb558Sryan_chen #define ASPEED_RESET_RESERVED58	(58)
1121fbb558Sryan_chen #define ASPEED_RESET_RESERVED57	(57)
1221fbb558Sryan_chen #define ASPEED_RESET_SD			(56)
1321fbb558Sryan_chen #define ASPEED_RESET_ADC		(55)
1421fbb558Sryan_chen #define ASPEED_RESET_JTAG_MASTER2	(54)
1521fbb558Sryan_chen #define ASPEED_RESET_MAC4		(53)
1621fbb558Sryan_chen #define ASPEED_RESET_MAC3		(52)
1721fbb558Sryan_chen #define ASPEED_RESET_RESERVE51	(51)
1821fbb558Sryan_chen #define ASPEED_RESET_RESERVE50	(50)
1921fbb558Sryan_chen #define ASPEED_RESET_RESERVE49	(49)
2021fbb558Sryan_chen #define ASPEED_RESET_RESERVE48	(48)
2121fbb558Sryan_chen #define ASPEED_RESET_RESERVE47	(47)
2221fbb558Sryan_chen #define ASPEED_RESET_RESERVE46	(46)
2321fbb558Sryan_chen #define ASPEED_RESET_I3C5		(45)
2421fbb558Sryan_chen #define ASPEED_RESET_I3C4		(44)
2521fbb558Sryan_chen #define ASPEED_RESET_I3C3		(43)
2621fbb558Sryan_chen #define ASPEED_RESET_I3C2		(42)
2721fbb558Sryan_chen #define ASPEED_RESET_I3C1		(41)
2821fbb558Sryan_chen #define ASPEED_RESET_I3C0		(40)
2921fbb558Sryan_chen #define ASPEED_RESET_I3C_DMA	(39)
3021fbb558Sryan_chen #define ASPEED_RESET_RESERVED38	(38)
3121fbb558Sryan_chen #define ASPEED_RESET_PWM		(37)
3221fbb558Sryan_chen #define ASPEED_RESET_PECI		(36)
3321fbb558Sryan_chen #define ASPEED_RESET_MII		(35)
3421fbb558Sryan_chen #define ASPEED_RESET_I2C		(34)
3521fbb558Sryan_chen #define ASPEED_RESET_RESERVED33	(33)
36*c8ffe8c6Sryan_chen #define ASPEED_RESET_LPC_ESPI	(32)
3721fbb558Sryan_chen 
3821fbb558Sryan_chen #define ASPEED_RESET_RESERVED31	(31)
3921fbb558Sryan_chen #define ASPEED_RESET_RESERVED30	(30)
4021fbb558Sryan_chen #define ASPEED_RESET_RESERVED29	(29)
4121fbb558Sryan_chen #define ASPEED_RESET_DP			(28)
42*c8ffe8c6Sryan_chen #define ASPEED_RESET_RC_XDMA	(27)
4321fbb558Sryan_chen #define ASPEED_RESET_GRAPHICS	(26)
44*c8ffe8c6Sryan_chen #define ASPEED_RESET_DEV_XDMA	(25)
45*c8ffe8c6Sryan_chen #define ASPEED_RESET_DEV_MCTP	(24)
46*c8ffe8c6Sryan_chen #define ASPEED_RESET_RC_MCTP	(23)
4721fbb558Sryan_chen #define ASPEED_RESET_JTAG_MASTER	(22)
4821fbb558Sryan_chen #define ASPEED_RESET_PCIE_DEV_O		(21)
4921fbb558Sryan_chen #define ASPEED_RESET_PCIE_DEV_OEN	(20)
5021fbb558Sryan_chen #define ASPEED_RESET_PCIE_RC_O		(19)
5121fbb558Sryan_chen #define ASPEED_RESET_PCIE_RC_OEN	(18)
5221fbb558Sryan_chen #define ASPEED_RESET_RESERVED17	(17)
5321fbb558Sryan_chen #define ASEPPD_RESET_EMMC		(16)
5421fbb558Sryan_chen #define ASPEED_RESET_UHCI		(15)
5521fbb558Sryan_chen #define ASPEED_RESET_EHCI_P1	(14)
5621fbb558Sryan_chen #define ASPEED_RESET_CRT		(13)
5721fbb558Sryan_chen #define ASPEED_RESET_MAC2		(12)
5821fbb558Sryan_chen #define ASPEED_RESET_MAC1		(11)
5921fbb558Sryan_chen #define ASPEED_RESET_RESERVED10	(10)
6021fbb558Sryan_chen #define ASPEED_RESET_RVAS		(9)
6121fbb558Sryan_chen #define ASPEED_RESET_PCI_VGA	(8)
6221fbb558Sryan_chen #define ASPEED_RESET_2D			(7)
6321fbb558Sryan_chen #define ASPEED_RESET_VIDEO		(6)
6421fbb558Sryan_chen #define ASPEED_RESET_PCI_DP		(5)
6521fbb558Sryan_chen #define ASPEED_RESET_HACE		(4)
6621fbb558Sryan_chen #define ASPEED_RESET_EHCI_P2	(3)
6721fbb558Sryan_chen #define ASPEED_RESET_RESERVED2	(2)
6821fbb558Sryan_chen #define ASPEED_RESET_AHB		(1)
6921fbb558Sryan_chen #define ASPEED_RESET_SDRAM		(0)
7021fbb558Sryan_chen 
71*c8ffe8c6Sryan_chen #endif  /* _MACH_ASPEED_AST2600_RESET_H_ */
72