1*f88c345bSryan_chen /* SPDX-License-Identifier: GPL-2.0+ */ 2*f88c345bSryan_chen 3*f88c345bSryan_chen #ifndef _ABI_MACH_ASPEED_AST2400_RESET_H_ 4*f88c345bSryan_chen #define _ABI_MACH_ASPEED_AST2400_RESET_H_ 5*f88c345bSryan_chen 6*f88c345bSryan_chen /* 7*f88c345bSryan_chen * The values are intentionally layed out as flags in 8*f88c345bSryan_chen * WDT reset parameter. 9*f88c345bSryan_chen */ 10*f88c345bSryan_chen #define ASPEED_RESET_CRT1 (37) 11*f88c345bSryan_chen #define ASPEED_RESET_RESERVED36 (36) 12*f88c345bSryan_chen #define ASPEED_RESET_RESERVED35 (35) 13*f88c345bSryan_chen #define ASPEED_RESET_RESERVED34 (34) 14*f88c345bSryan_chen #define ASPEED_RESET_RESERVED33 (33) 15*f88c345bSryan_chen #define ASPEED_RESET_RESERVED32 (32) 16*f88c345bSryan_chen 17*f88c345bSryan_chen #define ASPEED_RESET_RESERVED31 (31) 18*f88c345bSryan_chen #define ASPEED_RESET_RESERVED30 (30) 19*f88c345bSryan_chen #define ASPEED_RESET_RESERVED29 (29) 20*f88c345bSryan_chen #define ASPEED_RESET_RESERVED28 (28) 21*f88c345bSryan_chen #define ASPEED_RESET_RESERVED27 (27) 22*f88c345bSryan_chen #define ASPEED_RESET_RESERVED26 (26) 23*f88c345bSryan_chen #define ASPEED_RESET_XDMA (25) 24*f88c345bSryan_chen #define ASPEED_RESET_MCTP (24) 25*f88c345bSryan_chen #define ASPEED_RESET_ADC (23) 26*f88c345bSryan_chen #define ASPEED_RESET_JTAG_MASTER (22) 27*f88c345bSryan_chen #define ASPEED_RESET_RESERVED21 (21) 28*f88c345bSryan_chen #define ASPEED_RESET_RESERVED20 (20) 29*f88c345bSryan_chen #define ASPEED_RESET_RESERVED19 (19) 30*f88c345bSryan_chen #define ASPEED_RESET_MIC (18) 31*f88c345bSryan_chen #define ASPEED_RESET_RESERVED17 (17) 32*f88c345bSryan_chen #define ASEPPD_RESET_SDIO (16) 33*f88c345bSryan_chen #define ASPEED_RESET_UHCI (15) 34*f88c345bSryan_chen #define ASPEED_RESET_EHCI_P1 (14) 35*f88c345bSryan_chen #define ASPEED_RESET_CRT (13) 36*f88c345bSryan_chen #define ASPEED_RESET_MAC2 (12) 37*f88c345bSryan_chen #define ASPEED_RESET_MAC1 (11) 38*f88c345bSryan_chen #define ASPEED_RESET_PECI (10) 39*f88c345bSryan_chen #define ASPEED_RESET_PWM (9) 40*f88c345bSryan_chen #define ASPEED_RESET_PCI_VGA (8) 41*f88c345bSryan_chen #define ASPEED_RESET_2D (7) 42*f88c345bSryan_chen #define ASPEED_RESET_VIDEO (6) 43*f88c345bSryan_chen #define ASPEED_RESET_LPC_ESPI (5) 44*f88c345bSryan_chen #define ASPEED_RESET_HACE (4) 45*f88c345bSryan_chen #define ASPEED_RESET_EHCI_P2 (3) 46*f88c345bSryan_chen #define ASPEED_RESET_I2C (2) 47*f88c345bSryan_chen #define ASPEED_RESET_AHB (1) 48*f88c345bSryan_chen #define ASPEED_RESET_SDRAM (0) 49*f88c345bSryan_chen 50*f88c345bSryan_chen #endif /* _ABI_MACH_ASPEED_AST2400_RESET_H_ */ 51