1f88c345bSryan_chen /* SPDX-License-Identifier: GPL-2.0+ */ 2f88c345bSryan_chen 3f88c345bSryan_chen #ifndef _ABI_MACH_ASPEED_AST2400_RESET_H_ 4f88c345bSryan_chen #define _ABI_MACH_ASPEED_AST2400_RESET_H_ 5f88c345bSryan_chen 6f88c345bSryan_chen /* 7f88c345bSryan_chen * The values are intentionally layed out as flags in 8f88c345bSryan_chen * WDT reset parameter. 9f88c345bSryan_chen */ 10f88c345bSryan_chen #define ASPEED_RESET_RESERVED31 (31) 11f88c345bSryan_chen #define ASPEED_RESET_RESERVED30 (30) 12f88c345bSryan_chen #define ASPEED_RESET_RESERVED29 (29) 13f88c345bSryan_chen #define ASPEED_RESET_RESERVED28 (28) 14f88c345bSryan_chen #define ASPEED_RESET_RESERVED27 (27) 15f88c345bSryan_chen #define ASPEED_RESET_RESERVED26 (26) 16f88c345bSryan_chen #define ASPEED_RESET_XDMA (25) 17f88c345bSryan_chen #define ASPEED_RESET_MCTP (24) 18f88c345bSryan_chen #define ASPEED_RESET_ADC (23) 19f88c345bSryan_chen #define ASPEED_RESET_JTAG_MASTER (22) 20f88c345bSryan_chen #define ASPEED_RESET_RESERVED21 (21) 21f88c345bSryan_chen #define ASPEED_RESET_RESERVED20 (20) 22f88c345bSryan_chen #define ASPEED_RESET_RESERVED19 (19) 23f88c345bSryan_chen #define ASPEED_RESET_MIC (18) 24f88c345bSryan_chen #define ASPEED_RESET_RESERVED17 (17) 25f88c345bSryan_chen #define ASEPPD_RESET_SDIO (16) 26f88c345bSryan_chen #define ASPEED_RESET_UHCI (15) 27f88c345bSryan_chen #define ASPEED_RESET_EHCI_P1 (14) 28f88c345bSryan_chen #define ASPEED_RESET_CRT (13) 29f88c345bSryan_chen #define ASPEED_RESET_MAC2 (12) 30f88c345bSryan_chen #define ASPEED_RESET_MAC1 (11) 31f88c345bSryan_chen #define ASPEED_RESET_PECI (10) 32f88c345bSryan_chen #define ASPEED_RESET_PWM (9) 33f88c345bSryan_chen #define ASPEED_RESET_PCI_VGA (8) 34f88c345bSryan_chen #define ASPEED_RESET_2D (7) 35f88c345bSryan_chen #define ASPEED_RESET_VIDEO (6) 36*8c16b8afSryan_chen #define ASPEED_RESET_LPC (5) 37f88c345bSryan_chen #define ASPEED_RESET_HACE (4) 38f88c345bSryan_chen #define ASPEED_RESET_EHCI_P2 (3) 39f88c345bSryan_chen #define ASPEED_RESET_I2C (2) 40f88c345bSryan_chen #define ASPEED_RESET_AHB (1) 41f88c345bSryan_chen #define ASPEED_RESET_SDRAM (0) 42f88c345bSryan_chen 43f88c345bSryan_chen #endif /* _ABI_MACH_ASPEED_AST2400_RESET_H_ */ 44