1*7b9cb494SStephen Warren /* 2*7b9cb494SStephen Warren * Copyright (c) 2015-2016, NVIDIA CORPORATION. 3*7b9cb494SStephen Warren * 4*7b9cb494SStephen Warren * SPDX-License-Identifier: GPL-2.0 5*7b9cb494SStephen Warren */ 6*7b9cb494SStephen Warren 7*7b9cb494SStephen Warren #ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H 8*7b9cb494SStephen Warren #define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H 9*7b9cb494SStephen Warren 10*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_AUD 0 11*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_DFD 1 12*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_DISP 2 13*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_DISPB 3 14*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_DISPC 4 15*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_ISPA 5 16*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_NVDEC 6 17*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_NVJPG 7 18*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_MPE 8 19*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_PCX 9 20*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_SAX 10 21*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_VE 11 22*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_VIC 12 23*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_XUSBA 13 24*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_XUSBB 14 25*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_XUSBC 15 26*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_GPU 43 27*7b9cb494SStephen Warren #define TEGRA186_POWER_DOMAIN_MAX 44 28*7b9cb494SStephen Warren 29*7b9cb494SStephen Warren #endif 30