1 #ifndef DT_BINDINGS_STM32_SDRAM_H
2 #define DT_BINDINGS_STM32_SDRAM_H
3 
4 #define NO_COL_8	0x0
5 #define NO_COL_9	0x1
6 #define NO_COL_10	0x2
7 #define NO_COL_11	0x3
8 
9 #define NO_ROW_11	0x0
10 #define NO_ROW_12	0x1
11 #define NO_ROW_13	0x2
12 
13 #define MWIDTH_8	0x0
14 #define MWIDTH_16	0x1
15 #define MWIDTH_32	0x2
16 #define BANKS_2		0x0
17 #define BANKS_4		0x1
18 #define CAS_1		0x1
19 #define CAS_2		0x2
20 #define CAS_3		0x3
21 #define SDCLK_DIS	0x0
22 #define SDCLK_2		0x2
23 #define SDCLK_3		0x3
24 #define RD_BURST_EN	0x1
25 #define RD_BURST_DIS	0x0
26 #define RD_PIPE_DL_0	0x0
27 #define RD_PIPE_DL_1	0x1
28 #define RD_PIPE_DL_2	0x2
29 
30 /* Timing = value +1 cycles */
31 #define TMRD_1		(1 - 1)
32 #define TMRD_2		(2 - 1)
33 #define TMRD_3		(3 - 1)
34 #define TXSR_1		(1 - 1)
35 #define TXSR_6		(6 - 1)
36 #define TXSR_7		(7 - 1)
37 #define TRAS_1		(1 - 1)
38 #define TRAS_4		(4 - 1)
39 #define TRC_6		(6 - 1)
40 #define TWR_1		(1 - 1)
41 #define TWR_2		(2 - 1)
42 #define TRP_2		(2 - 1)
43 #define TRCD_1		(1 - 1)
44 #define TRCD_2		(2 - 1)
45 
46 #endif
47