1*6f967856SSimon Glass /* 2*6f967856SSimon Glass * This header provides macros for at91 dma bindings. 3*6f967856SSimon Glass * 4*6f967856SSimon Glass * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com> 5*6f967856SSimon Glass * 6*6f967856SSimon Glass * GPLv2 only 7*6f967856SSimon Glass */ 8*6f967856SSimon Glass 9*6f967856SSimon Glass #ifndef __DT_BINDINGS_AT91_DMA_H__ 10*6f967856SSimon Glass #define __DT_BINDINGS_AT91_DMA_H__ 11*6f967856SSimon Glass 12*6f967856SSimon Glass /* ---------- HDMAC ---------- */ 13*6f967856SSimon Glass 14*6f967856SSimon Glass /* 15*6f967856SSimon Glass * Source and/or destination peripheral ID 16*6f967856SSimon Glass */ 17*6f967856SSimon Glass #define AT91_DMA_CFG_PER_ID_MASK (0xff) 18*6f967856SSimon Glass #define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) 19*6f967856SSimon Glass 20*6f967856SSimon Glass /* 21*6f967856SSimon Glass * FIFO configuration: it defines when a request is serviced. 22*6f967856SSimon Glass */ 23*6f967856SSimon Glass #define AT91_DMA_CFG_FIFOCFG_OFFSET (8) 24*6f967856SSimon Glass #define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) 25*6f967856SSimon Glass #define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ 26*6f967856SSimon Glass #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ 27*6f967856SSimon Glass #define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ 28*6f967856SSimon Glass 29*6f967856SSimon Glass 30*6f967856SSimon Glass /* ---------- XDMAC ---------- */ 31*6f967856SSimon Glass #define AT91_XDMAC_DT_MEM_IF_MASK (0x1) 32*6f967856SSimon Glass #define AT91_XDMAC_DT_MEM_IF_OFFSET (13) 33*6f967856SSimon Glass #define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ 34*6f967856SSimon Glass << AT91_XDMAC_DT_MEM_IF_OFFSET) 35*6f967856SSimon Glass #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ 36*6f967856SSimon Glass & AT91_XDMAC_DT_MEM_IF_MASK) 37*6f967856SSimon Glass 38*6f967856SSimon Glass #define AT91_XDMAC_DT_PER_IF_MASK (0x1) 39*6f967856SSimon Glass #define AT91_XDMAC_DT_PER_IF_OFFSET (14) 40*6f967856SSimon Glass #define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ 41*6f967856SSimon Glass << AT91_XDMAC_DT_PER_IF_OFFSET) 42*6f967856SSimon Glass #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ 43*6f967856SSimon Glass & AT91_XDMAC_DT_PER_IF_MASK) 44*6f967856SSimon Glass 45*6f967856SSimon Glass #define AT91_XDMAC_DT_PERID_MASK (0x7f) 46*6f967856SSimon Glass #define AT91_XDMAC_DT_PERID_OFFSET (24) 47*6f967856SSimon Glass #define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ 48*6f967856SSimon Glass << AT91_XDMAC_DT_PERID_OFFSET) 49*6f967856SSimon Glass #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ 50*6f967856SSimon Glass & AT91_XDMAC_DT_PERID_MASK) 51*6f967856SSimon Glass 52*6f967856SSimon Glass #endif /* __DT_BINDINGS_AT91_DMA_H__ */ 53