1/* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * Copyright 2016 Toradex AG 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This file is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/clock/imx7d-clock.h> 45#include <dt-bindings/gpio/gpio.h> 46#include <dt-bindings/input/input.h> 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include "imx7d-pinfunc.h" 49 50/ { 51 #address-cells = <1>; 52 #size-cells = <1>; 53 /* 54 * The decompressor and also some bootloaders rely on a 55 * pre-existing /chosen node to be available to insert the 56 * command line and merge other ATAGS info. 57 * Also for U-Boot there must be a pre-existing /memory node. 58 */ 59 chosen {}; 60 memory { device_type = "memory"; reg = <0 0>; }; 61 62 aliases { 63 gpio0 = &gpio1; 64 gpio1 = &gpio2; 65 gpio2 = &gpio3; 66 gpio3 = &gpio4; 67 gpio4 = &gpio5; 68 gpio5 = &gpio6; 69 gpio6 = &gpio7; 70 i2c0 = &i2c1; 71 i2c1 = &i2c2; 72 i2c2 = &i2c3; 73 i2c3 = &i2c4; 74 mmc0 = &usdhc1; 75 mmc1 = &usdhc2; 76 mmc2 = &usdhc3; 77 serial0 = &uart1; 78 serial1 = &uart2; 79 serial2 = &uart3; 80 serial3 = &uart4; 81 serial4 = &uart5; 82 serial5 = &uart6; 83 serial6 = &uart7; 84 spi0 = &ecspi1; 85 spi1 = &ecspi2; 86 spi2 = &ecspi3; 87 spi3 = &ecspi4; 88 }; 89 90 cpus { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 94 cpu0: cpu@0 { 95 compatible = "arm,cortex-a7"; 96 device_type = "cpu"; 97 reg = <0>; 98 clock-frequency = <792000000>; 99 clock-latency = <61036>; /* two CLK32 periods */ 100 clocks = <&clks IMX7D_CLK_ARM>; 101 }; 102 }; 103 104 ckil: clock-cki { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <32768>; 108 clock-output-names = "ckil"; 109 }; 110 111 osc: clock-osc { 112 compatible = "fixed-clock"; 113 #clock-cells = <0>; 114 clock-frequency = <24000000>; 115 clock-output-names = "osc"; 116 }; 117 118 soc { 119 #address-cells = <1>; 120 #size-cells = <1>; 121 compatible = "simple-bus"; 122 interrupt-parent = <&intc>; 123 ranges; 124 125 funnel@30041000 { 126 compatible = "arm,coresight-funnel", "arm,primecell"; 127 reg = <0x30041000 0x1000>; 128 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 129 clock-names = "apb_pclk"; 130 131 ca_funnel_ports: ports { 132 #address-cells = <1>; 133 #size-cells = <0>; 134 135 /* funnel input ports */ 136 port@0 { 137 reg = <0>; 138 ca_funnel_in_port0: endpoint { 139 slave-mode; 140 remote-endpoint = <&etm0_out_port>; 141 }; 142 }; 143 144 /* funnel output port */ 145 port@2 { 146 reg = <0>; 147 ca_funnel_out_port0: endpoint { 148 remote-endpoint = <&hugo_funnel_in_port0>; 149 }; 150 }; 151 152 /* the other input ports are not connect to anything */ 153 }; 154 }; 155 156 etm@3007c000 { 157 compatible = "arm,coresight-etm3x", "arm,primecell"; 158 reg = <0x3007c000 0x1000>; 159 cpu = <&cpu0>; 160 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 161 clock-names = "apb_pclk"; 162 163 port { 164 etm0_out_port: endpoint { 165 remote-endpoint = <&ca_funnel_in_port0>; 166 }; 167 }; 168 }; 169 170 funnel@30083000 { 171 compatible = "arm,coresight-funnel", "arm,primecell"; 172 reg = <0x30083000 0x1000>; 173 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 174 clock-names = "apb_pclk"; 175 176 ports { 177 #address-cells = <1>; 178 #size-cells = <0>; 179 180 /* funnel input ports */ 181 port@0 { 182 reg = <0>; 183 hugo_funnel_in_port0: endpoint { 184 slave-mode; 185 remote-endpoint = <&ca_funnel_out_port0>; 186 }; 187 }; 188 189 port@1 { 190 reg = <1>; 191 hugo_funnel_in_port1: endpoint { 192 slave-mode; /* M4 input */ 193 }; 194 }; 195 196 port@2 { 197 reg = <0>; 198 hugo_funnel_out_port0: endpoint { 199 remote-endpoint = <&etf_in_port>; 200 }; 201 }; 202 203 /* the other input ports are not connect to anything */ 204 }; 205 }; 206 207 etf@30084000 { 208 compatible = "arm,coresight-tmc", "arm,primecell"; 209 reg = <0x30084000 0x1000>; 210 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 211 clock-names = "apb_pclk"; 212 213 ports { 214 #address-cells = <1>; 215 #size-cells = <0>; 216 217 port@0 { 218 reg = <0>; 219 etf_in_port: endpoint { 220 slave-mode; 221 remote-endpoint = <&hugo_funnel_out_port0>; 222 }; 223 }; 224 225 port@1 { 226 reg = <0>; 227 etf_out_port: endpoint { 228 remote-endpoint = <&replicator_in_port0>; 229 }; 230 }; 231 }; 232 }; 233 234 etr@30086000 { 235 compatible = "arm,coresight-tmc", "arm,primecell"; 236 reg = <0x30086000 0x1000>; 237 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 238 clock-names = "apb_pclk"; 239 240 port { 241 etr_in_port: endpoint { 242 slave-mode; 243 remote-endpoint = <&replicator_out_port1>; 244 }; 245 }; 246 }; 247 248 tpiu@30087000 { 249 compatible = "arm,coresight-tpiu", "arm,primecell"; 250 reg = <0x30087000 0x1000>; 251 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 252 clock-names = "apb_pclk"; 253 254 port { 255 tpiu_in_port: endpoint { 256 slave-mode; 257 remote-endpoint = <&replicator_out_port1>; 258 }; 259 }; 260 }; 261 262 replicator { 263 /* 264 * non-configurable replicators don't show up on the 265 * AMBA bus. As such no need to add "arm,primecell" 266 */ 267 compatible = "arm,coresight-replicator"; 268 269 ports { 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 /* replicator output ports */ 274 port@0 { 275 reg = <0>; 276 replicator_out_port0: endpoint { 277 remote-endpoint = <&tpiu_in_port>; 278 }; 279 }; 280 281 port@1 { 282 reg = <1>; 283 replicator_out_port1: endpoint { 284 remote-endpoint = <&etr_in_port>; 285 }; 286 }; 287 288 /* replicator input port */ 289 port@2 { 290 reg = <0>; 291 replicator_in_port0: endpoint { 292 slave-mode; 293 remote-endpoint = <&etf_out_port>; 294 }; 295 }; 296 }; 297 }; 298 299 intc: interrupt-controller@31001000 { 300 compatible = "arm,cortex-a7-gic"; 301 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 302 #interrupt-cells = <3>; 303 interrupt-controller; 304 reg = <0x31001000 0x1000>, 305 <0x31002000 0x2000>, 306 <0x31004000 0x2000>, 307 <0x31006000 0x2000>; 308 }; 309 310 timer { 311 compatible = "arm,armv7-timer"; 312 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 313 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 314 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 315 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 316 }; 317 318 aips1: aips-bus@30000000 { 319 compatible = "fsl,aips-bus", "simple-bus"; 320 #address-cells = <1>; 321 #size-cells = <1>; 322 reg = <0x30000000 0x400000>; 323 ranges; 324 325 gpio1: gpio@30200000 { 326 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 327 reg = <0x30200000 0x10000>; 328 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 329 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 330 gpio-controller; 331 #gpio-cells = <2>; 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 335 }; 336 337 gpio2: gpio@30210000 { 338 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 339 reg = <0x30210000 0x10000>; 340 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 342 gpio-controller; 343 #gpio-cells = <2>; 344 interrupt-controller; 345 #interrupt-cells = <2>; 346 gpio-ranges = <&iomuxc 0 13 32>; 347 }; 348 349 gpio3: gpio@30220000 { 350 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 351 reg = <0x30220000 0x10000>; 352 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 354 gpio-controller; 355 #gpio-cells = <2>; 356 interrupt-controller; 357 #interrupt-cells = <2>; 358 gpio-ranges = <&iomuxc 0 45 29>; 359 }; 360 361 gpio4: gpio@30230000 { 362 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 363 reg = <0x30230000 0x10000>; 364 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 366 gpio-controller; 367 #gpio-cells = <2>; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 gpio-ranges = <&iomuxc 0 74 24>; 371 }; 372 373 gpio5: gpio@30240000 { 374 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 375 reg = <0x30240000 0x10000>; 376 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 interrupt-controller; 381 #interrupt-cells = <2>; 382 gpio-ranges = <&iomuxc 0 98 18>; 383 }; 384 385 gpio6: gpio@30250000 { 386 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 387 reg = <0x30250000 0x10000>; 388 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 390 gpio-controller; 391 #gpio-cells = <2>; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 gpio-ranges = <&iomuxc 0 116 23>; 395 }; 396 397 gpio7: gpio@30260000 { 398 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 399 reg = <0x30260000 0x10000>; 400 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 402 gpio-controller; 403 #gpio-cells = <2>; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 gpio-ranges = <&iomuxc 0 139 16>; 407 }; 408 409 wdog1: wdog@30280000 { 410 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 411 reg = <0x30280000 0x10000>; 412 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 414 }; 415 416 wdog2: wdog@30290000 { 417 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 418 reg = <0x30290000 0x10000>; 419 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 421 status = "disabled"; 422 }; 423 424 wdog3: wdog@302a0000 { 425 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 426 reg = <0x302a0000 0x10000>; 427 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 429 status = "disabled"; 430 }; 431 432 wdog4: wdog@302b0000 { 433 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 434 reg = <0x302b0000 0x10000>; 435 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 437 status = "disabled"; 438 }; 439 440 iomuxc_lpsr: iomuxc-lpsr@302c0000 { 441 compatible = "fsl,imx7d-iomuxc-lpsr"; 442 reg = <0x302c0000 0x10000>; 443 fsl,input-sel = <&iomuxc>; 444 }; 445 446 gpt1: gpt@302d0000 { 447 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 448 reg = <0x302d0000 0x10000>; 449 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&clks IMX7D_CLK_DUMMY>, 451 <&clks IMX7D_GPT1_ROOT_CLK>; 452 clock-names = "ipg", "per"; 453 }; 454 455 gpt2: gpt@302e0000 { 456 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 457 reg = <0x302e0000 0x10000>; 458 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clks IMX7D_CLK_DUMMY>, 460 <&clks IMX7D_GPT2_ROOT_CLK>; 461 clock-names = "ipg", "per"; 462 status = "disabled"; 463 }; 464 465 gpt3: gpt@302f0000 { 466 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 467 reg = <0x302f0000 0x10000>; 468 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clks IMX7D_CLK_DUMMY>, 470 <&clks IMX7D_GPT3_ROOT_CLK>; 471 clock-names = "ipg", "per"; 472 status = "disabled"; 473 }; 474 475 gpt4: gpt@30300000 { 476 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 477 reg = <0x30300000 0x10000>; 478 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&clks IMX7D_CLK_DUMMY>, 480 <&clks IMX7D_GPT4_ROOT_CLK>; 481 clock-names = "ipg", "per"; 482 status = "disabled"; 483 }; 484 485 iomuxc: iomuxc@30330000 { 486 compatible = "fsl,imx7d-iomuxc"; 487 reg = <0x30330000 0x10000>; 488 }; 489 490 gpr: iomuxc-gpr@30340000 { 491 compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; 492 reg = <0x30340000 0x10000>; 493 }; 494 495 ocotp: ocotp-ctrl@30350000 { 496 compatible = "fsl,imx7d-ocotp", "syscon"; 497 reg = <0x30350000 0x10000>; 498 clocks = <&clks IMX7D_OCOTP_CLK>; 499 }; 500 501 anatop: anatop@30360000 { 502 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 503 "syscon", "simple-bus"; 504 reg = <0x30360000 0x10000>; 505 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 507 508 reg_1p0d: regulator-vdd1p0d { 509 compatible = "fsl,anatop-regulator"; 510 regulator-name = "vdd1p0d"; 511 regulator-min-microvolt = <800000>; 512 regulator-max-microvolt = <1200000>; 513 anatop-reg-offset = <0x210>; 514 anatop-vol-bit-shift = <8>; 515 anatop-vol-bit-width = <5>; 516 anatop-min-bit-val = <8>; 517 anatop-min-voltage = <800000>; 518 anatop-max-voltage = <1200000>; 519 }; 520 }; 521 522 snvs: snvs@30370000 { 523 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 524 reg = <0x30370000 0x10000>; 525 526 snvs_rtc: snvs-rtc-lp { 527 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 528 regmap = <&snvs>; 529 offset = <0x34>; 530 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 532 }; 533 534 snvs_poweroff: snvs-poweroff { 535 compatible = "syscon-poweroff"; 536 regmap = <&snvs>; 537 offset = <0x38>; 538 mask = <0x60>; 539 }; 540 541 snvs_pwrkey: snvs-powerkey { 542 compatible = "fsl,sec-v4.0-pwrkey"; 543 regmap = <&snvs>; 544 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 545 linux,keycode = <KEY_POWER>; 546 wakeup-source; 547 }; 548 }; 549 550 clks: ccm@30380000 { 551 compatible = "fsl,imx7d-ccm"; 552 reg = <0x30380000 0x10000>; 553 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 555 #clock-cells = <1>; 556 clocks = <&ckil>, <&osc>; 557 clock-names = "ckil", "osc"; 558 }; 559 560 src: src@30390000 { 561 compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; 562 reg = <0x30390000 0x10000>; 563 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 564 #reset-cells = <1>; 565 }; 566 }; 567 568 aips2: aips-bus@30400000 { 569 compatible = "fsl,aips-bus", "simple-bus"; 570 #address-cells = <1>; 571 #size-cells = <1>; 572 reg = <0x30400000 0x400000>; 573 ranges; 574 575 adc1: adc@30610000 { 576 compatible = "fsl,imx7d-adc"; 577 reg = <0x30610000 0x10000>; 578 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 580 clock-names = "adc"; 581 status = "disabled"; 582 }; 583 584 adc2: adc@30620000 { 585 compatible = "fsl,imx7d-adc"; 586 reg = <0x30620000 0x10000>; 587 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 589 clock-names = "adc"; 590 status = "disabled"; 591 }; 592 593 ecspi4: ecspi@30630000 { 594 #address-cells = <1>; 595 #size-cells = <0>; 596 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 597 reg = <0x30630000 0x10000>; 598 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 600 <&clks IMX7D_ECSPI4_ROOT_CLK>; 601 clock-names = "ipg", "per"; 602 status = "disabled"; 603 }; 604 605 pwm1: pwm@30660000 { 606 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 607 reg = <0x30660000 0x10000>; 608 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 610 <&clks IMX7D_PWM1_ROOT_CLK>; 611 clock-names = "ipg", "per"; 612 #pwm-cells = <2>; 613 status = "disabled"; 614 }; 615 616 pwm2: pwm@30670000 { 617 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 618 reg = <0x30670000 0x10000>; 619 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 621 <&clks IMX7D_PWM2_ROOT_CLK>; 622 clock-names = "ipg", "per"; 623 #pwm-cells = <2>; 624 status = "disabled"; 625 }; 626 627 pwm3: pwm@30680000 { 628 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 629 reg = <0x30680000 0x10000>; 630 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 632 <&clks IMX7D_PWM3_ROOT_CLK>; 633 clock-names = "ipg", "per"; 634 #pwm-cells = <2>; 635 status = "disabled"; 636 }; 637 638 pwm4: pwm@30690000 { 639 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 640 reg = <0x30690000 0x10000>; 641 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 643 <&clks IMX7D_PWM4_ROOT_CLK>; 644 clock-names = "ipg", "per"; 645 #pwm-cells = <2>; 646 status = "disabled"; 647 }; 648 649 lcdif: lcdif@30730000 { 650 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; 651 reg = <0x30730000 0x10000>; 652 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 654 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 655 clock-names = "pix", "axi"; 656 status = "disabled"; 657 }; 658 }; 659 660 aips3: aips-bus@30800000 { 661 compatible = "fsl,aips-bus", "simple-bus"; 662 #address-cells = <1>; 663 #size-cells = <1>; 664 reg = <0x30800000 0x400000>; 665 ranges; 666 667 ecspi1: ecspi@30820000 { 668 #address-cells = <1>; 669 #size-cells = <0>; 670 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 671 reg = <0x30820000 0x10000>; 672 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 674 <&clks IMX7D_ECSPI1_ROOT_CLK>; 675 clock-names = "ipg", "per"; 676 status = "disabled"; 677 }; 678 679 ecspi2: ecspi@30830000 { 680 #address-cells = <1>; 681 #size-cells = <0>; 682 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 683 reg = <0x30830000 0x10000>; 684 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 686 <&clks IMX7D_ECSPI2_ROOT_CLK>; 687 clock-names = "ipg", "per"; 688 status = "disabled"; 689 }; 690 691 ecspi3: ecspi@30840000 { 692 #address-cells = <1>; 693 #size-cells = <0>; 694 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 695 reg = <0x30840000 0x10000>; 696 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 698 <&clks IMX7D_ECSPI3_ROOT_CLK>; 699 clock-names = "ipg", "per"; 700 status = "disabled"; 701 }; 702 703 uart1: serial@30860000 { 704 compatible = "fsl,imx7d-uart", 705 "fsl,imx6q-uart"; 706 reg = <0x30860000 0x10000>; 707 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 709 <&clks IMX7D_UART1_ROOT_CLK>; 710 clock-names = "ipg", "per"; 711 status = "disabled"; 712 }; 713 714 uart2: serial@30890000 { 715 compatible = "fsl,imx7d-uart", 716 "fsl,imx6q-uart"; 717 reg = <0x30890000 0x10000>; 718 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 720 <&clks IMX7D_UART2_ROOT_CLK>; 721 clock-names = "ipg", "per"; 722 status = "disabled"; 723 }; 724 725 uart3: serial@30880000 { 726 compatible = "fsl,imx7d-uart", 727 "fsl,imx6q-uart"; 728 reg = <0x30880000 0x10000>; 729 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 731 <&clks IMX7D_UART3_ROOT_CLK>; 732 clock-names = "ipg", "per"; 733 status = "disabled"; 734 }; 735 736 sai1: sai@308a0000 { 737 #sound-dai-cells = <0>; 738 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 739 reg = <0x308a0000 0x10000>; 740 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 742 <&clks IMX7D_SAI1_ROOT_CLK>, 743 <&clks IMX7D_CLK_DUMMY>, 744 <&clks IMX7D_CLK_DUMMY>; 745 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 746 dma-names = "rx", "tx"; 747 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 748 status = "disabled"; 749 }; 750 751 sai2: sai@308b0000 { 752 #sound-dai-cells = <0>; 753 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 754 reg = <0x308b0000 0x10000>; 755 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 757 <&clks IMX7D_SAI2_ROOT_CLK>, 758 <&clks IMX7D_CLK_DUMMY>, 759 <&clks IMX7D_CLK_DUMMY>; 760 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 761 dma-names = "rx", "tx"; 762 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 763 status = "disabled"; 764 }; 765 766 sai3: sai@308c0000 { 767 #sound-dai-cells = <0>; 768 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 769 reg = <0x308c0000 0x10000>; 770 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 772 <&clks IMX7D_SAI3_ROOT_CLK>, 773 <&clks IMX7D_CLK_DUMMY>, 774 <&clks IMX7D_CLK_DUMMY>; 775 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 776 dma-names = "rx", "tx"; 777 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 778 status = "disabled"; 779 }; 780 781 flexcan1: can@30a00000 { 782 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 783 reg = <0x30a00000 0x10000>; 784 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&clks IMX7D_CLK_DUMMY>, 786 <&clks IMX7D_CAN1_ROOT_CLK>; 787 clock-names = "ipg", "per"; 788 status = "disabled"; 789 }; 790 791 flexcan2: can@30a10000 { 792 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 793 reg = <0x30a10000 0x10000>; 794 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&clks IMX7D_CLK_DUMMY>, 796 <&clks IMX7D_CAN2_ROOT_CLK>; 797 clock-names = "ipg", "per"; 798 status = "disabled"; 799 }; 800 801 i2c1: i2c@30a20000 { 802 #address-cells = <1>; 803 #size-cells = <0>; 804 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 805 reg = <0x30a20000 0x10000>; 806 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 808 status = "disabled"; 809 }; 810 811 i2c2: i2c@30a30000 { 812 #address-cells = <1>; 813 #size-cells = <0>; 814 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 815 reg = <0x30a30000 0x10000>; 816 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 818 status = "disabled"; 819 }; 820 821 i2c3: i2c@30a40000 { 822 #address-cells = <1>; 823 #size-cells = <0>; 824 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 825 reg = <0x30a40000 0x10000>; 826 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 828 status = "disabled"; 829 }; 830 831 i2c4: i2c@30a50000 { 832 #address-cells = <1>; 833 #size-cells = <0>; 834 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 835 reg = <0x30a50000 0x10000>; 836 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 838 status = "disabled"; 839 }; 840 841 uart4: serial@30a60000 { 842 compatible = "fsl,imx7d-uart", 843 "fsl,imx6q-uart"; 844 reg = <0x30a60000 0x10000>; 845 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 847 <&clks IMX7D_UART4_ROOT_CLK>; 848 clock-names = "ipg", "per"; 849 status = "disabled"; 850 }; 851 852 uart5: serial@30a70000 { 853 compatible = "fsl,imx7d-uart", 854 "fsl,imx6q-uart"; 855 reg = <0x30a70000 0x10000>; 856 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 858 <&clks IMX7D_UART5_ROOT_CLK>; 859 clock-names = "ipg", "per"; 860 status = "disabled"; 861 }; 862 863 uart6: serial@30a80000 { 864 compatible = "fsl,imx7d-uart", 865 "fsl,imx6q-uart"; 866 reg = <0x30a80000 0x10000>; 867 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 869 <&clks IMX7D_UART6_ROOT_CLK>; 870 clock-names = "ipg", "per"; 871 status = "disabled"; 872 }; 873 874 uart7: serial@30a90000 { 875 compatible = "fsl,imx7d-uart", 876 "fsl,imx6q-uart"; 877 reg = <0x30a90000 0x10000>; 878 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 880 <&clks IMX7D_UART7_ROOT_CLK>; 881 clock-names = "ipg", "per"; 882 status = "disabled"; 883 }; 884 885 usbotg1: usb@30b10000 { 886 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 887 reg = <0x30b10000 0x200>; 888 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&clks IMX7D_USB_CTRL_CLK>; 890 fsl,usbphy = <&usbphynop1>; 891 fsl,usbmisc = <&usbmisc1 0>; 892 phy-clkgate-delay-us = <400>; 893 status = "disabled"; 894 }; 895 896 usbh: usb@30b30000 { 897 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 898 reg = <0x30b30000 0x200>; 899 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&clks IMX7D_USB_CTRL_CLK>; 901 fsl,usbphy = <&usbphynop3>; 902 fsl,usbmisc = <&usbmisc3 0>; 903 phy_type = "hsic"; 904 dr_mode = "host"; 905 phy-clkgate-delay-us = <400>; 906 status = "disabled"; 907 }; 908 909 usbmisc1: usbmisc@30b10200 { 910 #index-cells = <1>; 911 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 912 reg = <0x30b10200 0x200>; 913 }; 914 915 usbmisc3: usbmisc@30b30200 { 916 #index-cells = <1>; 917 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 918 reg = <0x30b30200 0x200>; 919 }; 920 921 usbphynop1: usbphynop1 { 922 compatible = "usb-nop-xceiv"; 923 clocks = <&clks IMX7D_USB_PHY1_CLK>; 924 clock-names = "main_clk"; 925 }; 926 927 usbphynop3: usbphynop3 { 928 compatible = "usb-nop-xceiv"; 929 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 930 clock-names = "main_clk"; 931 }; 932 933 usdhc1: usdhc@30b40000 { 934 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 935 reg = <0x30b40000 0x10000>; 936 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&clks IMX7D_CLK_DUMMY>, 938 <&clks IMX7D_CLK_DUMMY>, 939 <&clks IMX7D_USDHC1_ROOT_CLK>; 940 clock-names = "ipg", "ahb", "per"; 941 bus-width = <4>; 942 status = "disabled"; 943 }; 944 945 usdhc2: usdhc@30b50000 { 946 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 947 reg = <0x30b50000 0x10000>; 948 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 949 clocks = <&clks IMX7D_CLK_DUMMY>, 950 <&clks IMX7D_CLK_DUMMY>, 951 <&clks IMX7D_USDHC2_ROOT_CLK>; 952 clock-names = "ipg", "ahb", "per"; 953 bus-width = <4>; 954 status = "disabled"; 955 }; 956 957 usdhc3: usdhc@30b60000 { 958 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 959 reg = <0x30b60000 0x10000>; 960 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&clks IMX7D_CLK_DUMMY>, 962 <&clks IMX7D_CLK_DUMMY>, 963 <&clks IMX7D_USDHC3_ROOT_CLK>; 964 clock-names = "ipg", "ahb", "per"; 965 bus-width = <4>; 966 status = "disabled"; 967 }; 968 969 sdma: sdma@30bd0000 { 970 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 971 reg = <0x30bd0000 0x10000>; 972 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&clks IMX7D_SDMA_CORE_CLK>, 974 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 975 clock-names = "ipg", "ahb"; 976 #dma-cells = <3>; 977 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 978 }; 979 980 fec1: ethernet@30be0000 { 981 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 982 reg = <0x30be0000 0x10000>; 983 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, 987 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 988 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 989 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 990 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 991 clock-names = "ipg", "ahb", "ptp", 992 "enet_clk_ref", "enet_out"; 993 fsl,num-tx-queues=<3>; 994 fsl,num-rx-queues=<3>; 995 status = "disabled"; 996 }; 997 }; 998 }; 999}; 1000