xref: /openbmc/u-boot/arch/arm/dts/imx7s.dtsi (revision e93db9b6)
1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 * Copyright 2016 Toradex AG
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This file is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License as
12 *     published by the Free Software Foundation; either version 2 of the
13 *     License, or (at your option) any later version.
14 *
15 *     This file is distributed in the hope that it will be useful,
16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 *     GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 *  b) Permission is hereby granted, free of charge, to any person
23 *     obtaining a copy of this software and associated documentation
24 *     files (the "Software"), to deal in the Software without
25 *     restriction, including without limitation the rights to use,
26 *     copy, modify, merge, publish, distribute, sublicense, and/or
27 *     sell copies of the Software, and to permit persons to whom the
28 *     Software is furnished to do so, subject to the following
29 *     conditions:
30 *
31 *     The above copyright notice and this permission notice shall be
32 *     included in all copies or substantial portions of the Software.
33 *
34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 *     OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include <dt-bindings/clock/imx7d-clock.h>
45#include <dt-bindings/power/imx7-power.h>
46#include <dt-bindings/gpio/gpio.h>
47#include <dt-bindings/input/input.h>
48#include <dt-bindings/interrupt-controller/arm-gic.h>
49#include "imx7d-pinfunc.h"
50
51/ {
52	#address-cells = <1>;
53	#size-cells = <1>;
54	/*
55	 * The decompressor and also some bootloaders rely on a
56	 * pre-existing /chosen node to be available to insert the
57	 * command line and merge other ATAGS info.
58	 * Also for U-Boot there must be a pre-existing /memory node.
59	 */
60	chosen {};
61	memory { device_type = "memory"; };
62
63	aliases {
64		gpio0 = &gpio1;
65		gpio1 = &gpio2;
66		gpio2 = &gpio3;
67		gpio3 = &gpio4;
68		gpio4 = &gpio5;
69		gpio5 = &gpio6;
70		gpio6 = &gpio7;
71		i2c0 = &i2c1;
72		i2c1 = &i2c2;
73		i2c2 = &i2c3;
74		i2c3 = &i2c4;
75		mmc0 = &usdhc1;
76		mmc1 = &usdhc2;
77		mmc2 = &usdhc3;
78		serial0 = &uart1;
79		serial1 = &uart2;
80		serial2 = &uart3;
81		serial3 = &uart4;
82		serial4 = &uart5;
83		serial5 = &uart6;
84		serial6 = &uart7;
85		spi0 = &ecspi1;
86		spi1 = &ecspi2;
87		spi2 = &ecspi3;
88		spi3 = &ecspi4;
89	};
90
91	cpus {
92		#address-cells = <1>;
93		#size-cells = <0>;
94
95		cpu0: cpu@0 {
96			compatible = "arm,cortex-a7";
97			device_type = "cpu";
98			reg = <0>;
99			clock-frequency = <792000000>;
100			clock-latency = <61036>; /* two CLK32 periods */
101			clocks = <&clks IMX7D_CLK_ARM>;
102		};
103	};
104
105	ckil: clock-cki {
106		compatible = "fixed-clock";
107		#clock-cells = <0>;
108		clock-frequency = <32768>;
109		clock-output-names = "ckil";
110	};
111
112	osc: clock-osc {
113		compatible = "fixed-clock";
114		#clock-cells = <0>;
115		clock-frequency = <24000000>;
116		clock-output-names = "osc";
117	};
118
119	usbphynop1: usbphynop1 {
120		compatible = "usb-nop-xceiv";
121		clocks = <&clks IMX7D_USB_PHY1_CLK>;
122		clock-names = "main_clk";
123		#phy-cells = <0>;
124	};
125
126	usbphynop3: usbphynop3 {
127		compatible = "usb-nop-xceiv";
128		clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
129		clock-names = "main_clk";
130		#phy-cells = <0>;
131	};
132
133	pmu {
134		compatible = "arm,cortex-a7-pmu";
135		interrupt-parent = <&gpc>;
136		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
137		interrupt-affinity = <&cpu0>;
138	};
139
140	replicator {
141		/*
142		 * non-configurable replicators don't show up on the
143		 * AMBA bus.  As such no need to add "arm,primecell"
144		 */
145		compatible = "arm,coresight-replicator";
146
147		ports {
148			#address-cells = <1>;
149			#size-cells = <0>;
150				/* replicator output ports */
151			port@0 {
152				reg = <0>;
153				replicator_out_port0: endpoint {
154					remote-endpoint = <&tpiu_in_port>;
155				};
156			};
157
158			port@1 {
159				reg = <1>;
160				replicator_out_port1: endpoint {
161					remote-endpoint = <&etr_in_port>;
162				};
163			};
164
165			/* replicator input port */
166			port@2 {
167				reg = <0>;
168				replicator_in_port0: endpoint {
169					slave-mode;
170					remote-endpoint = <&etf_out_port>;
171				};
172			};
173		};
174	};
175
176	timer {
177		compatible = "arm,armv7-timer";
178		interrupt-parent = <&intc>;
179		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
180			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
181			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
182			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
183	};
184
185	soc {
186		#address-cells = <1>;
187		#size-cells = <1>;
188		compatible = "simple-bus";
189		interrupt-parent = <&gpc>;
190		ranges;
191
192		funnel@30041000 {
193			compatible = "arm,coresight-funnel", "arm,primecell";
194			reg = <0x30041000 0x1000>;
195			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
196			clock-names = "apb_pclk";
197
198			ca_funnel_ports: ports {
199				#address-cells = <1>;
200				#size-cells = <0>;
201
202				/* funnel input ports */
203				port@0 {
204					reg = <0>;
205					ca_funnel_in_port0: endpoint {
206						slave-mode;
207						remote-endpoint = <&etm0_out_port>;
208					};
209				};
210
211				/* funnel output port */
212				port@2 {
213					reg = <0>;
214					ca_funnel_out_port0: endpoint {
215						remote-endpoint = <&hugo_funnel_in_port0>;
216					};
217				};
218
219				/* the other input ports are not connect to anything */
220			};
221		};
222
223		etm@3007c000 {
224			compatible = "arm,coresight-etm3x", "arm,primecell";
225			reg = <0x3007c000 0x1000>;
226			cpu = <&cpu0>;
227			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
228			clock-names = "apb_pclk";
229
230			port {
231				etm0_out_port: endpoint {
232					remote-endpoint = <&ca_funnel_in_port0>;
233				};
234			};
235		};
236
237		funnel@30083000 {
238			compatible = "arm,coresight-funnel", "arm,primecell";
239			reg = <0x30083000 0x1000>;
240			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
241			clock-names = "apb_pclk";
242
243			ports {
244				#address-cells = <1>;
245				#size-cells = <0>;
246
247				/* funnel input ports */
248				port@0 {
249					reg = <0>;
250					hugo_funnel_in_port0: endpoint {
251						slave-mode;
252						remote-endpoint = <&ca_funnel_out_port0>;
253					};
254				};
255
256				port@1 {
257					reg = <1>;
258					hugo_funnel_in_port1: endpoint {
259						slave-mode; /* M4 input */
260					};
261				};
262
263				port@2 {
264					reg = <0>;
265					hugo_funnel_out_port0: endpoint {
266						remote-endpoint = <&etf_in_port>;
267					};
268				};
269
270				/* the other input ports are not connect to anything */
271			};
272		};
273
274		etf@30084000 {
275			compatible = "arm,coresight-tmc", "arm,primecell";
276			reg = <0x30084000 0x1000>;
277			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
278			clock-names = "apb_pclk";
279
280			ports {
281				#address-cells = <1>;
282				#size-cells = <0>;
283
284				port@0 {
285					reg = <0>;
286					etf_in_port: endpoint {
287						slave-mode;
288						remote-endpoint = <&hugo_funnel_out_port0>;
289					};
290				};
291
292				port@1 {
293					reg = <0>;
294					etf_out_port: endpoint {
295						remote-endpoint = <&replicator_in_port0>;
296					};
297				};
298			};
299		};
300
301		etr@30086000 {
302			compatible = "arm,coresight-tmc", "arm,primecell";
303			reg = <0x30086000 0x1000>;
304			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
305			clock-names = "apb_pclk";
306
307			port {
308				etr_in_port: endpoint {
309					slave-mode;
310					remote-endpoint = <&replicator_out_port1>;
311				};
312			};
313		};
314
315		tpiu@30087000 {
316			compatible = "arm,coresight-tpiu", "arm,primecell";
317			reg = <0x30087000 0x1000>;
318			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
319			clock-names = "apb_pclk";
320
321			port {
322				tpiu_in_port: endpoint {
323					slave-mode;
324					remote-endpoint = <&replicator_out_port1>;
325				};
326			};
327		};
328
329		intc: interrupt-controller@31001000 {
330			compatible = "arm,cortex-a7-gic";
331			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
332			#interrupt-cells = <3>;
333			interrupt-controller;
334			interrupt-parent = <&intc>;
335			reg = <0x31001000 0x1000>,
336			      <0x31002000 0x2000>,
337			      <0x31004000 0x2000>,
338			      <0x31006000 0x2000>;
339		};
340
341		aips1: aips-bus@30000000 {
342			compatible = "fsl,aips-bus", "simple-bus";
343			#address-cells = <1>;
344			#size-cells = <1>;
345			reg = <0x30000000 0x400000>;
346			ranges;
347
348			gpio1: gpio@30200000 {
349				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
350				reg = <0x30200000 0x10000>;
351				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
352					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
353				gpio-controller;
354				#gpio-cells = <2>;
355				interrupt-controller;
356				#interrupt-cells = <2>;
357				gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
358			};
359
360			gpio2: gpio@30210000 {
361				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
362				reg = <0x30210000 0x10000>;
363				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
364					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
365				gpio-controller;
366				#gpio-cells = <2>;
367				interrupt-controller;
368				#interrupt-cells = <2>;
369				gpio-ranges = <&iomuxc 0 13 32>;
370			};
371
372			gpio3: gpio@30220000 {
373				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
374				reg = <0x30220000 0x10000>;
375				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
376					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
377				gpio-controller;
378				#gpio-cells = <2>;
379				interrupt-controller;
380				#interrupt-cells = <2>;
381				gpio-ranges = <&iomuxc 0 45 29>;
382			};
383
384			gpio4: gpio@30230000 {
385				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
386				reg = <0x30230000 0x10000>;
387				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
388					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
389				gpio-controller;
390				#gpio-cells = <2>;
391				interrupt-controller;
392				#interrupt-cells = <2>;
393				gpio-ranges = <&iomuxc 0 74 24>;
394			};
395
396			gpio5: gpio@30240000 {
397				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
398				reg = <0x30240000 0x10000>;
399				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
400					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
401				gpio-controller;
402				#gpio-cells = <2>;
403				interrupt-controller;
404				#interrupt-cells = <2>;
405				gpio-ranges = <&iomuxc 0 98 18>;
406			};
407
408			gpio6: gpio@30250000 {
409				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
410				reg = <0x30250000 0x10000>;
411				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
412					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
413				gpio-controller;
414				#gpio-cells = <2>;
415				interrupt-controller;
416				#interrupt-cells = <2>;
417				gpio-ranges = <&iomuxc 0 116 23>;
418			};
419
420			gpio7: gpio@30260000 {
421				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
422				reg = <0x30260000 0x10000>;
423				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
424					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
425				gpio-controller;
426				#gpio-cells = <2>;
427				interrupt-controller;
428				#interrupt-cells = <2>;
429				gpio-ranges = <&iomuxc 0 139 16>;
430			};
431
432			wdog1: wdog@30280000 {
433				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
434				reg = <0x30280000 0x10000>;
435				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
436				clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
437			};
438
439			wdog2: wdog@30290000 {
440				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
441				reg = <0x30290000 0x10000>;
442				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
443				clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
444				status = "disabled";
445			};
446
447			wdog3: wdog@302a0000 {
448				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
449				reg = <0x302a0000 0x10000>;
450				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
451				clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
452				status = "disabled";
453			};
454
455			wdog4: wdog@302b0000 {
456				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
457				reg = <0x302b0000 0x10000>;
458				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
459				clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
460				status = "disabled";
461			};
462
463			iomuxc_lpsr: iomuxc-lpsr@302c0000 {
464				compatible = "fsl,imx7d-iomuxc-lpsr";
465				reg = <0x302c0000 0x10000>;
466				fsl,input-sel = <&iomuxc>;
467			};
468
469			gpt1: gpt@302d0000 {
470				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
471				reg = <0x302d0000 0x10000>;
472				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
473				clocks = <&clks IMX7D_CLK_DUMMY>,
474					 <&clks IMX7D_GPT1_ROOT_CLK>;
475				clock-names = "ipg", "per";
476			};
477
478			gpt2: gpt@302e0000 {
479				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
480				reg = <0x302e0000 0x10000>;
481				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
482				clocks = <&clks IMX7D_CLK_DUMMY>,
483					 <&clks IMX7D_GPT2_ROOT_CLK>;
484				clock-names = "ipg", "per";
485				status = "disabled";
486			};
487
488			gpt3: gpt@302f0000 {
489				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
490				reg = <0x302f0000 0x10000>;
491				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
492				clocks = <&clks IMX7D_CLK_DUMMY>,
493					 <&clks IMX7D_GPT3_ROOT_CLK>;
494				clock-names = "ipg", "per";
495				status = "disabled";
496			};
497
498			gpt4: gpt@30300000 {
499				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
500				reg = <0x30300000 0x10000>;
501				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
502				clocks = <&clks IMX7D_CLK_DUMMY>,
503					 <&clks IMX7D_GPT4_ROOT_CLK>;
504				clock-names = "ipg", "per";
505				status = "disabled";
506			};
507
508			kpp: kpp@30320000 {
509				compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
510				reg = <0x30320000 0x10000>;
511				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
512				clocks = <&clks IMX7D_KPP_ROOT_CLK>;
513				status = "disabled";
514			};
515
516			iomuxc: iomuxc@30330000 {
517				compatible = "fsl,imx7d-iomuxc";
518				reg = <0x30330000 0x10000>;
519			};
520
521			gpr: iomuxc-gpr@30340000 {
522				compatible = "fsl,imx7d-iomuxc-gpr",
523					"fsl,imx6q-iomuxc-gpr", "syscon";
524				reg = <0x30340000 0x10000>;
525			};
526
527			ocotp: ocotp-ctrl@30350000 {
528				#address-cells = <1>;
529				#size-cells = <1>;
530				compatible = "fsl,imx7d-ocotp", "syscon";
531				reg = <0x30350000 0x10000>;
532				clocks = <&clks IMX7D_OCOTP_CLK>;
533
534				tempmon_calib: calib@3c {
535					reg = <0x3c 0x4>;
536				};
537
538				tempmon_temp_grade: temp-grade@10 {
539					reg = <0x10 0x4>;
540				};
541			};
542
543			tempmon: tempmon {
544				compatible = "fsl,imx7d-tempmon";
545				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
546				fsl,tempmon =<&anatop>;
547				nvmem-cells = <&tempmon_calib>,
548					<&tempmon_temp_grade>;
549				nvmem-cell-names = "calib", "temp_grade";
550				clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
551			};
552
553			anatop: anatop@30360000 {
554				compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
555					"syscon", "simple-bus";
556				reg = <0x30360000 0x10000>;
557				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
558					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
559				#address-cells = <1>;
560				#size-cells = <0>;
561
562				reg_1p0d: regulator-vdd1p0d@30360210 {
563					reg = <0x30360210>;
564					compatible = "fsl,anatop-regulator";
565					regulator-name = "vdd1p0d";
566					regulator-min-microvolt = <800000>;
567					regulator-max-microvolt = <1200000>;
568					anatop-reg-offset = <0x210>;
569					anatop-vol-bit-shift = <8>;
570					anatop-vol-bit-width = <5>;
571					anatop-min-bit-val = <8>;
572					anatop-min-voltage = <800000>;
573					anatop-max-voltage = <1200000>;
574					anatop-enable-bit = <0>;
575				};
576			};
577
578			snvs: snvs@30370000 {
579				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
580				reg = <0x30370000 0x10000>;
581
582				snvs_rtc: snvs-rtc-lp {
583					compatible = "fsl,sec-v4.0-mon-rtc-lp";
584					regmap = <&snvs>;
585					offset = <0x34>;
586					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
587						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
588					clocks = <&clks IMX7D_SNVS_CLK>;
589					clock-names = "snvs-rtc";
590				};
591
592				snvs_poweroff: snvs-poweroff {
593					compatible = "syscon-poweroff";
594					regmap = <&snvs>;
595					offset = <0x38>;
596					value = <0x60>;
597					mask = <0x60>;
598				};
599
600				snvs_pwrkey: snvs-powerkey {
601					compatible = "fsl,sec-v4.0-pwrkey";
602					regmap = <&snvs>;
603					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
604					linux,keycode = <KEY_POWER>;
605					wakeup-source;
606				};
607			};
608
609			clks: ccm@30380000 {
610				compatible = "fsl,imx7d-ccm";
611				reg = <0x30380000 0x10000>;
612				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
613					     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
614				#clock-cells = <1>;
615				clocks = <&ckil>, <&osc>;
616				clock-names = "ckil", "osc";
617			};
618
619			src: src@30390000 {
620				compatible = "fsl,imx7d-src", "syscon";
621				reg = <0x30390000 0x10000>;
622				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
623				#reset-cells = <1>;
624			};
625
626			gpc: gpc@303a0000 {
627				compatible = "fsl,imx7d-gpc";
628				reg = <0x303a0000 0x10000>;
629				interrupt-controller;
630				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
631				#interrupt-cells = <3>;
632				interrupt-parent = <&intc>;
633				#power-domain-cells = <1>;
634
635				pgc {
636					#address-cells = <1>;
637					#size-cells = <0>;
638
639					pgc_pcie_phy: pgc-power-domain@1 {
640						#power-domain-cells = <0>;
641						reg = <1>;
642						power-supply = <&reg_1p0d>;
643					};
644				};
645			};
646		};
647
648		aips2: aips-bus@30400000 {
649			compatible = "fsl,aips-bus", "simple-bus";
650			#address-cells = <1>;
651			#size-cells = <1>;
652			reg = <0x30400000 0x400000>;
653			ranges;
654
655			adc1: adc@30610000 {
656				compatible = "fsl,imx7d-adc";
657				reg = <0x30610000 0x10000>;
658				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
659				clocks = <&clks IMX7D_ADC_ROOT_CLK>;
660				clock-names = "adc";
661				status = "disabled";
662			};
663
664			adc2: adc@30620000 {
665				compatible = "fsl,imx7d-adc";
666				reg = <0x30620000 0x10000>;
667				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
668				clocks = <&clks IMX7D_ADC_ROOT_CLK>;
669				clock-names = "adc";
670				status = "disabled";
671			};
672
673			ecspi4: ecspi@30630000 {
674				#address-cells = <1>;
675				#size-cells = <0>;
676				compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
677				reg = <0x30630000 0x10000>;
678				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
679				clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
680					<&clks IMX7D_ECSPI4_ROOT_CLK>;
681				clock-names = "ipg", "per";
682				status = "disabled";
683			};
684
685			pwm1: pwm@30660000 {
686				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
687				reg = <0x30660000 0x10000>;
688				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
689				clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
690					 <&clks IMX7D_PWM1_ROOT_CLK>;
691				clock-names = "ipg", "per";
692				#pwm-cells = <3>;
693				status = "disabled";
694			};
695
696			pwm2: pwm@30670000 {
697				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
698				reg = <0x30670000 0x10000>;
699				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
700				clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
701					 <&clks IMX7D_PWM2_ROOT_CLK>;
702				clock-names = "ipg", "per";
703				#pwm-cells = <3>;
704				status = "disabled";
705			};
706
707			pwm3: pwm@30680000 {
708				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
709				reg = <0x30680000 0x10000>;
710				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
711				clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
712					 <&clks IMX7D_PWM3_ROOT_CLK>;
713				clock-names = "ipg", "per";
714				#pwm-cells = <3>;
715				status = "disabled";
716			};
717
718			pwm4: pwm@30690000 {
719				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
720				reg = <0x30690000 0x10000>;
721				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
722				clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
723					 <&clks IMX7D_PWM4_ROOT_CLK>;
724				clock-names = "ipg", "per";
725				#pwm-cells = <3>;
726				status = "disabled";
727			};
728
729			lcdif: lcdif@30730000 {
730				compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
731				reg = <0x30730000 0x10000>;
732				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
733				clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
734					<&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
735				clock-names = "pix", "axi";
736				status = "disabled";
737			};
738		};
739
740		aips3: aips-bus@30800000 {
741			compatible = "fsl,aips-bus", "simple-bus";
742			#address-cells = <1>;
743			#size-cells = <1>;
744			reg = <0x30800000 0x400000>;
745			ranges;
746
747			spba-bus@30800000 {
748				compatible = "fsl,spba-bus", "simple-bus";
749				#address-cells = <1>;
750				#size-cells = <1>;
751				reg = <0x30800000 0x100000>;
752				ranges;
753
754				ecspi1: ecspi@30820000 {
755					#address-cells = <1>;
756					#size-cells = <0>;
757					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
758					reg = <0x30820000 0x10000>;
759					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
760					clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
761						<&clks IMX7D_ECSPI1_ROOT_CLK>;
762					clock-names = "ipg", "per";
763					status = "disabled";
764				};
765
766				ecspi2: ecspi@30830000 {
767					#address-cells = <1>;
768					#size-cells = <0>;
769					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
770					reg = <0x30830000 0x10000>;
771					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
772					clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
773						<&clks IMX7D_ECSPI2_ROOT_CLK>;
774					clock-names = "ipg", "per";
775					status = "disabled";
776				};
777
778				ecspi3: ecspi@30840000 {
779					#address-cells = <1>;
780					#size-cells = <0>;
781					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
782					reg = <0x30840000 0x10000>;
783					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
784					clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
785						<&clks IMX7D_ECSPI3_ROOT_CLK>;
786					clock-names = "ipg", "per";
787					status = "disabled";
788				};
789
790				uart1: serial@30860000 {
791					compatible = "fsl,imx7d-uart",
792						     "fsl,imx6q-uart";
793					reg = <0x30860000 0x10000>;
794					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
795					clocks = <&clks IMX7D_UART1_ROOT_CLK>,
796						<&clks IMX7D_UART1_ROOT_CLK>;
797					clock-names = "ipg", "per";
798					status = "disabled";
799				};
800
801				uart2: serial@30890000 {
802					compatible = "fsl,imx7d-uart",
803						     "fsl,imx6q-uart";
804					reg = <0x30890000 0x10000>;
805					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
806					clocks = <&clks IMX7D_UART2_ROOT_CLK>,
807						<&clks IMX7D_UART2_ROOT_CLK>;
808					clock-names = "ipg", "per";
809					status = "disabled";
810				};
811
812				uart3: serial@30880000 {
813					compatible = "fsl,imx7d-uart",
814						     "fsl,imx6q-uart";
815					reg = <0x30880000 0x10000>;
816					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
817					clocks = <&clks IMX7D_UART3_ROOT_CLK>,
818						<&clks IMX7D_UART3_ROOT_CLK>;
819					clock-names = "ipg", "per";
820					status = "disabled";
821				};
822
823				sai1: sai@308a0000 {
824					#sound-dai-cells = <0>;
825					compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
826					reg = <0x308a0000 0x10000>;
827					interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
828					clocks = <&clks IMX7D_SAI1_IPG_CLK>,
829						 <&clks IMX7D_SAI1_ROOT_CLK>,
830						 <&clks IMX7D_CLK_DUMMY>,
831						 <&clks IMX7D_CLK_DUMMY>;
832					clock-names = "bus", "mclk1", "mclk2", "mclk3";
833					dma-names = "rx", "tx";
834					dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
835					status = "disabled";
836				};
837
838				sai2: sai@308b0000 {
839					#sound-dai-cells = <0>;
840					compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
841					reg = <0x308b0000 0x10000>;
842					interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
843					clocks = <&clks IMX7D_SAI2_IPG_CLK>,
844						 <&clks IMX7D_SAI2_ROOT_CLK>,
845						 <&clks IMX7D_CLK_DUMMY>,
846						 <&clks IMX7D_CLK_DUMMY>;
847					clock-names = "bus", "mclk1", "mclk2", "mclk3";
848					dma-names = "rx", "tx";
849					dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
850					status = "disabled";
851				};
852
853				sai3: sai@308c0000 {
854					#sound-dai-cells = <0>;
855					compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
856					reg = <0x308c0000 0x10000>;
857					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
858					clocks = <&clks IMX7D_SAI3_IPG_CLK>,
859						 <&clks IMX7D_SAI3_ROOT_CLK>,
860						 <&clks IMX7D_CLK_DUMMY>,
861						 <&clks IMX7D_CLK_DUMMY>;
862					clock-names = "bus", "mclk1", "mclk2", "mclk3";
863					dma-names = "rx", "tx";
864					dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
865					status = "disabled";
866				};
867			};
868
869			crypto: caam@30900000 {
870				compatible = "fsl,sec-v4.0";
871				#address-cells = <1>;
872				#size-cells = <1>;
873				reg = <0x30900000 0x40000>;
874				ranges = <0 0x30900000 0x40000>;
875				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
876				clocks = <&clks IMX7D_CAAM_CLK>,
877					 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
878				clock-names = "ipg", "aclk";
879
880				sec_jr0: jr0@1000 {
881					compatible = "fsl,sec-v4.0-job-ring";
882					reg = <0x1000 0x1000>;
883					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
884				};
885
886				sec_jr1: jr1@2000 {
887					compatible = "fsl,sec-v4.0-job-ring";
888					reg = <0x2000 0x1000>;
889					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
890				};
891
892				sec_jr2: jr1@3000 {
893					compatible = "fsl,sec-v4.0-job-ring";
894					reg = <0x3000 0x1000>;
895					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
896				};
897			};
898
899			flexcan1: can@30a00000 {
900				compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
901				reg = <0x30a00000 0x10000>;
902				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
903				clocks = <&clks IMX7D_CLK_DUMMY>,
904					<&clks IMX7D_CAN1_ROOT_CLK>;
905				clock-names = "ipg", "per";
906				status = "disabled";
907			};
908
909			flexcan2: can@30a10000 {
910				compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
911				reg = <0x30a10000 0x10000>;
912				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
913				clocks = <&clks IMX7D_CLK_DUMMY>,
914					<&clks IMX7D_CAN2_ROOT_CLK>;
915				clock-names = "ipg", "per";
916				status = "disabled";
917			};
918
919			i2c1: i2c@30a20000 {
920				#address-cells = <1>;
921				#size-cells = <0>;
922				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
923				reg = <0x30a20000 0x10000>;
924				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
925				clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
926				status = "disabled";
927			};
928
929			i2c2: i2c@30a30000 {
930				#address-cells = <1>;
931				#size-cells = <0>;
932				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
933				reg = <0x30a30000 0x10000>;
934				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
935				clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
936				status = "disabled";
937			};
938
939			i2c3: i2c@30a40000 {
940				#address-cells = <1>;
941				#size-cells = <0>;
942				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
943				reg = <0x30a40000 0x10000>;
944				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
945				clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
946				status = "disabled";
947			};
948
949			i2c4: i2c@30a50000 {
950				#address-cells = <1>;
951				#size-cells = <0>;
952				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
953				reg = <0x30a50000 0x10000>;
954				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
955				clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
956				status = "disabled";
957			};
958
959			uart4: serial@30a60000 {
960				compatible = "fsl,imx7d-uart",
961					     "fsl,imx6q-uart";
962				reg = <0x30a60000 0x10000>;
963				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
964				clocks = <&clks IMX7D_UART4_ROOT_CLK>,
965					<&clks IMX7D_UART4_ROOT_CLK>;
966				clock-names = "ipg", "per";
967				status = "disabled";
968			};
969
970			uart5: serial@30a70000 {
971				compatible = "fsl,imx7d-uart",
972					     "fsl,imx6q-uart";
973				reg = <0x30a70000 0x10000>;
974				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
975				clocks = <&clks IMX7D_UART5_ROOT_CLK>,
976					<&clks IMX7D_UART5_ROOT_CLK>;
977				clock-names = "ipg", "per";
978				status = "disabled";
979			};
980
981			uart6: serial@30a80000 {
982				compatible = "fsl,imx7d-uart",
983					     "fsl,imx6q-uart";
984				reg = <0x30a80000 0x10000>;
985				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
986				clocks = <&clks IMX7D_UART6_ROOT_CLK>,
987					<&clks IMX7D_UART6_ROOT_CLK>;
988				clock-names = "ipg", "per";
989				status = "disabled";
990			};
991
992			uart7: serial@30a90000 {
993				compatible = "fsl,imx7d-uart",
994					     "fsl,imx6q-uart";
995				reg = <0x30a90000 0x10000>;
996				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
997				clocks = <&clks IMX7D_UART7_ROOT_CLK>,
998					<&clks IMX7D_UART7_ROOT_CLK>;
999				clock-names = "ipg", "per";
1000				status = "disabled";
1001			};
1002
1003			usbotg1: usb@30b10000 {
1004				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1005				reg = <0x30b10000 0x200>;
1006				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1007				clocks = <&clks IMX7D_USB_CTRL_CLK>;
1008				fsl,usbphy = <&usbphynop1>;
1009				fsl,usbmisc = <&usbmisc1 0>;
1010				phy-clkgate-delay-us = <400>;
1011				status = "disabled";
1012			};
1013
1014			usbh: usb@30b30000 {
1015				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1016				reg = <0x30b30000 0x200>;
1017				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1018				clocks = <&clks IMX7D_USB_CTRL_CLK>;
1019				fsl,usbphy = <&usbphynop3>;
1020				fsl,usbmisc = <&usbmisc3 0>;
1021				phy_type = "hsic";
1022				dr_mode = "host";
1023				phy-clkgate-delay-us = <400>;
1024				status = "disabled";
1025			};
1026
1027			usbmisc1: usbmisc@30b10200 {
1028				#index-cells = <1>;
1029				compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1030				reg = <0x30b10200 0x200>;
1031			};
1032
1033			usbmisc3: usbmisc@30b30200 {
1034				#index-cells = <1>;
1035				compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1036				reg = <0x30b30200 0x200>;
1037			};
1038
1039			usdhc1: usdhc@30b40000 {
1040				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1041				reg = <0x30b40000 0x10000>;
1042				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1043				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1044					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1045					<&clks IMX7D_USDHC1_ROOT_CLK>;
1046				clock-names = "ipg", "ahb", "per";
1047				bus-width = <4>;
1048				status = "disabled";
1049			};
1050
1051			usdhc2: usdhc@30b50000 {
1052				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1053				reg = <0x30b50000 0x10000>;
1054				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1055				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1056					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1057					<&clks IMX7D_USDHC2_ROOT_CLK>;
1058				clock-names = "ipg", "ahb", "per";
1059				bus-width = <4>;
1060				status = "disabled";
1061			};
1062
1063			usdhc3: usdhc@30b60000 {
1064				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1065				reg = <0x30b60000 0x10000>;
1066				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1067				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1068					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1069					<&clks IMX7D_USDHC3_ROOT_CLK>;
1070				clock-names = "ipg", "ahb", "per";
1071				bus-width = <4>;
1072				status = "disabled";
1073			};
1074
1075			sdma: sdma@30bd0000 {
1076				compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1077				reg = <0x30bd0000 0x10000>;
1078				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1079				clocks = <&clks IMX7D_SDMA_CORE_CLK>,
1080					 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1081				clock-names = "ipg", "ahb";
1082				#dma-cells = <3>;
1083				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1084			};
1085
1086			fec1: ethernet@30be0000 {
1087				compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1088				reg = <0x30be0000 0x10000>;
1089				interrupt-names = "int0", "int1", "int2", "pps";
1090				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1091					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1092					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1093					<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1094				clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1095					<&clks IMX7D_ENET_AXI_ROOT_CLK>,
1096					<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1097					<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1098					<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1099				clock-names = "ipg", "ahb", "ptp",
1100					"enet_clk_ref", "enet_out";
1101				fsl,num-tx-queues=<3>;
1102				fsl,num-rx-queues=<3>;
1103				status = "disabled";
1104			};
1105		};
1106
1107		dma_apbh: dma-apbh@33000000 {
1108			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1109			reg = <0x33000000 0x2000>;
1110			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1111				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1112				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1113				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1114			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1115			#dma-cells = <1>;
1116			dma-channels = <4>;
1117			clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1118		};
1119
1120		gpmi: gpmi-nand@33002000{
1121			compatible = "fsl,imx7d-gpmi-nand";
1122			#address-cells = <1>;
1123			#size-cells = <1>;
1124			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1125			reg-names = "gpmi-nand", "bch";
1126			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1127			interrupt-names = "bch";
1128			clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1129				<&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1130			clock-names = "gpmi_io", "gpmi_bch_apb";
1131			dmas = <&dma_apbh 0>;
1132			dma-names = "rx-tx";
1133			status = "disabled";
1134			assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1135			assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1136		};
1137	};
1138};
1139