1/* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * Copyright 2016 Toradex AG 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This file is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/clock/imx7d-clock.h> 45#include <dt-bindings/power/imx7-power.h> 46#include <dt-bindings/gpio/gpio.h> 47#include <dt-bindings/input/input.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include "imx7d-pinfunc.h" 50 51/ { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 /* 55 * The decompressor and also some bootloaders rely on a 56 * pre-existing /chosen node to be available to insert the 57 * command line and merge other ATAGS info. 58 * Also for U-Boot there must be a pre-existing /memory node. 59 */ 60 chosen {}; 61 memory { device_type = "memory"; }; 62 63 aliases { 64 gpio0 = &gpio1; 65 gpio1 = &gpio2; 66 gpio2 = &gpio3; 67 gpio3 = &gpio4; 68 gpio4 = &gpio5; 69 gpio5 = &gpio6; 70 gpio6 = &gpio7; 71 i2c0 = &i2c1; 72 i2c1 = &i2c2; 73 i2c2 = &i2c3; 74 i2c3 = &i2c4; 75 mmc0 = &usdhc1; 76 mmc1 = &usdhc2; 77 mmc2 = &usdhc3; 78 serial0 = &uart1; 79 serial1 = &uart2; 80 serial2 = &uart3; 81 serial3 = &uart4; 82 serial4 = &uart5; 83 serial5 = &uart6; 84 serial6 = &uart7; 85 spi0 = &qspi1; 86 spi1 = &ecspi1; 87 spi2 = &ecspi2; 88 spi3 = &ecspi3; 89 spi4 = &ecspi4; 90 }; 91 92 cpus { 93 #address-cells = <1>; 94 #size-cells = <0>; 95 96 cpu0: cpu@0 { 97 compatible = "arm,cortex-a7"; 98 device_type = "cpu"; 99 reg = <0>; 100 clock-frequency = <792000000>; 101 clock-latency = <61036>; /* two CLK32 periods */ 102 clocks = <&clks IMX7D_CLK_ARM>; 103 }; 104 }; 105 106 ckil: clock-cki { 107 compatible = "fixed-clock"; 108 #clock-cells = <0>; 109 clock-frequency = <32768>; 110 clock-output-names = "ckil"; 111 }; 112 113 osc: clock-osc { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <24000000>; 117 clock-output-names = "osc"; 118 }; 119 120 usbphynop1: usbphynop1 { 121 compatible = "usb-nop-xceiv"; 122 clocks = <&clks IMX7D_USB_PHY1_CLK>; 123 clock-names = "main_clk"; 124 #phy-cells = <0>; 125 }; 126 127 usbphynop3: usbphynop3 { 128 compatible = "usb-nop-xceiv"; 129 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 130 clock-names = "main_clk"; 131 #phy-cells = <0>; 132 }; 133 134 pmu { 135 compatible = "arm,cortex-a7-pmu"; 136 interrupt-parent = <&gpc>; 137 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 138 interrupt-affinity = <&cpu0>; 139 }; 140 141 replicator { 142 /* 143 * non-configurable replicators don't show up on the 144 * AMBA bus. As such no need to add "arm,primecell" 145 */ 146 compatible = "arm,coresight-replicator"; 147 148 ports { 149 #address-cells = <1>; 150 #size-cells = <0>; 151 /* replicator output ports */ 152 port@0 { 153 reg = <0>; 154 replicator_out_port0: endpoint { 155 remote-endpoint = <&tpiu_in_port>; 156 }; 157 }; 158 159 port@1 { 160 reg = <1>; 161 replicator_out_port1: endpoint { 162 remote-endpoint = <&etr_in_port>; 163 }; 164 }; 165 166 /* replicator input port */ 167 port@2 { 168 reg = <0>; 169 replicator_in_port0: endpoint { 170 slave-mode; 171 remote-endpoint = <&etf_out_port>; 172 }; 173 }; 174 }; 175 }; 176 177 timer { 178 compatible = "arm,armv7-timer"; 179 interrupt-parent = <&intc>; 180 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 181 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 182 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 183 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 184 }; 185 186 soc { 187 #address-cells = <1>; 188 #size-cells = <1>; 189 compatible = "simple-bus"; 190 interrupt-parent = <&gpc>; 191 ranges; 192 193 funnel@30041000 { 194 compatible = "arm,coresight-funnel", "arm,primecell"; 195 reg = <0x30041000 0x1000>; 196 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 197 clock-names = "apb_pclk"; 198 199 ca_funnel_ports: ports { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 203 /* funnel input ports */ 204 port@0 { 205 reg = <0>; 206 ca_funnel_in_port0: endpoint { 207 slave-mode; 208 remote-endpoint = <&etm0_out_port>; 209 }; 210 }; 211 212 /* funnel output port */ 213 port@2 { 214 reg = <0>; 215 ca_funnel_out_port0: endpoint { 216 remote-endpoint = <&hugo_funnel_in_port0>; 217 }; 218 }; 219 220 /* the other input ports are not connect to anything */ 221 }; 222 }; 223 224 etm@3007c000 { 225 compatible = "arm,coresight-etm3x", "arm,primecell"; 226 reg = <0x3007c000 0x1000>; 227 cpu = <&cpu0>; 228 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 229 clock-names = "apb_pclk"; 230 231 port { 232 etm0_out_port: endpoint { 233 remote-endpoint = <&ca_funnel_in_port0>; 234 }; 235 }; 236 }; 237 238 funnel@30083000 { 239 compatible = "arm,coresight-funnel", "arm,primecell"; 240 reg = <0x30083000 0x1000>; 241 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 242 clock-names = "apb_pclk"; 243 244 ports { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 248 /* funnel input ports */ 249 port@0 { 250 reg = <0>; 251 hugo_funnel_in_port0: endpoint { 252 slave-mode; 253 remote-endpoint = <&ca_funnel_out_port0>; 254 }; 255 }; 256 257 port@1 { 258 reg = <1>; 259 hugo_funnel_in_port1: endpoint { 260 slave-mode; /* M4 input */ 261 }; 262 }; 263 264 port@2 { 265 reg = <0>; 266 hugo_funnel_out_port0: endpoint { 267 remote-endpoint = <&etf_in_port>; 268 }; 269 }; 270 271 /* the other input ports are not connect to anything */ 272 }; 273 }; 274 275 etf@30084000 { 276 compatible = "arm,coresight-tmc", "arm,primecell"; 277 reg = <0x30084000 0x1000>; 278 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 279 clock-names = "apb_pclk"; 280 281 ports { 282 #address-cells = <1>; 283 #size-cells = <0>; 284 285 port@0 { 286 reg = <0>; 287 etf_in_port: endpoint { 288 slave-mode; 289 remote-endpoint = <&hugo_funnel_out_port0>; 290 }; 291 }; 292 293 port@1 { 294 reg = <0>; 295 etf_out_port: endpoint { 296 remote-endpoint = <&replicator_in_port0>; 297 }; 298 }; 299 }; 300 }; 301 302 etr@30086000 { 303 compatible = "arm,coresight-tmc", "arm,primecell"; 304 reg = <0x30086000 0x1000>; 305 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 306 clock-names = "apb_pclk"; 307 308 port { 309 etr_in_port: endpoint { 310 slave-mode; 311 remote-endpoint = <&replicator_out_port1>; 312 }; 313 }; 314 }; 315 316 tpiu@30087000 { 317 compatible = "arm,coresight-tpiu", "arm,primecell"; 318 reg = <0x30087000 0x1000>; 319 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 320 clock-names = "apb_pclk"; 321 322 port { 323 tpiu_in_port: endpoint { 324 slave-mode; 325 remote-endpoint = <&replicator_out_port1>; 326 }; 327 }; 328 }; 329 330 intc: interrupt-controller@31001000 { 331 compatible = "arm,cortex-a7-gic"; 332 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 333 #interrupt-cells = <3>; 334 interrupt-controller; 335 interrupt-parent = <&intc>; 336 reg = <0x31001000 0x1000>, 337 <0x31002000 0x2000>, 338 <0x31004000 0x2000>, 339 <0x31006000 0x2000>; 340 }; 341 342 aips1: aips-bus@30000000 { 343 compatible = "fsl,aips-bus", "simple-bus"; 344 #address-cells = <1>; 345 #size-cells = <1>; 346 reg = <0x30000000 0x400000>; 347 ranges; 348 349 gpio1: gpio@30200000 { 350 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 351 reg = <0x30200000 0x10000>; 352 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 353 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 354 gpio-controller; 355 #gpio-cells = <2>; 356 interrupt-controller; 357 #interrupt-cells = <2>; 358 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 359 }; 360 361 gpio2: gpio@30210000 { 362 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 363 reg = <0x30210000 0x10000>; 364 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 366 gpio-controller; 367 #gpio-cells = <2>; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 gpio-ranges = <&iomuxc 0 13 32>; 371 }; 372 373 gpio3: gpio@30220000 { 374 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 375 reg = <0x30220000 0x10000>; 376 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 interrupt-controller; 381 #interrupt-cells = <2>; 382 gpio-ranges = <&iomuxc 0 45 29>; 383 }; 384 385 gpio4: gpio@30230000 { 386 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 387 reg = <0x30230000 0x10000>; 388 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 390 gpio-controller; 391 #gpio-cells = <2>; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 gpio-ranges = <&iomuxc 0 74 24>; 395 }; 396 397 gpio5: gpio@30240000 { 398 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 399 reg = <0x30240000 0x10000>; 400 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 402 gpio-controller; 403 #gpio-cells = <2>; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 gpio-ranges = <&iomuxc 0 98 18>; 407 }; 408 409 gpio6: gpio@30250000 { 410 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 411 reg = <0x30250000 0x10000>; 412 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 414 gpio-controller; 415 #gpio-cells = <2>; 416 interrupt-controller; 417 #interrupt-cells = <2>; 418 gpio-ranges = <&iomuxc 0 116 23>; 419 }; 420 421 gpio7: gpio@30260000 { 422 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 423 reg = <0x30260000 0x10000>; 424 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 426 gpio-controller; 427 #gpio-cells = <2>; 428 interrupt-controller; 429 #interrupt-cells = <2>; 430 gpio-ranges = <&iomuxc 0 139 16>; 431 }; 432 433 wdog1: wdog@30280000 { 434 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 435 reg = <0x30280000 0x10000>; 436 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 438 }; 439 440 wdog2: wdog@30290000 { 441 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 442 reg = <0x30290000 0x10000>; 443 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 445 status = "disabled"; 446 }; 447 448 wdog3: wdog@302a0000 { 449 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 450 reg = <0x302a0000 0x10000>; 451 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 453 status = "disabled"; 454 }; 455 456 wdog4: wdog@302b0000 { 457 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 458 reg = <0x302b0000 0x10000>; 459 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 461 status = "disabled"; 462 }; 463 464 iomuxc_lpsr: iomuxc-lpsr@302c0000 { 465 compatible = "fsl,imx7d-iomuxc-lpsr"; 466 reg = <0x302c0000 0x10000>; 467 fsl,input-sel = <&iomuxc>; 468 }; 469 470 gpt1: gpt@302d0000 { 471 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 472 reg = <0x302d0000 0x10000>; 473 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&clks IMX7D_CLK_DUMMY>, 475 <&clks IMX7D_GPT1_ROOT_CLK>; 476 clock-names = "ipg", "per"; 477 }; 478 479 gpt2: gpt@302e0000 { 480 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 481 reg = <0x302e0000 0x10000>; 482 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&clks IMX7D_CLK_DUMMY>, 484 <&clks IMX7D_GPT2_ROOT_CLK>; 485 clock-names = "ipg", "per"; 486 status = "disabled"; 487 }; 488 489 gpt3: gpt@302f0000 { 490 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 491 reg = <0x302f0000 0x10000>; 492 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&clks IMX7D_CLK_DUMMY>, 494 <&clks IMX7D_GPT3_ROOT_CLK>; 495 clock-names = "ipg", "per"; 496 status = "disabled"; 497 }; 498 499 gpt4: gpt@30300000 { 500 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 501 reg = <0x30300000 0x10000>; 502 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&clks IMX7D_CLK_DUMMY>, 504 <&clks IMX7D_GPT4_ROOT_CLK>; 505 clock-names = "ipg", "per"; 506 status = "disabled"; 507 }; 508 509 kpp: kpp@30320000 { 510 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 511 reg = <0x30320000 0x10000>; 512 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&clks IMX7D_KPP_ROOT_CLK>; 514 status = "disabled"; 515 }; 516 517 iomuxc: iomuxc@30330000 { 518 compatible = "fsl,imx7d-iomuxc"; 519 reg = <0x30330000 0x10000>; 520 }; 521 522 gpr: iomuxc-gpr@30340000 { 523 compatible = "fsl,imx7d-iomuxc-gpr", 524 "fsl,imx6q-iomuxc-gpr", "syscon"; 525 reg = <0x30340000 0x10000>; 526 }; 527 528 ocotp: ocotp-ctrl@30350000 { 529 #address-cells = <1>; 530 #size-cells = <1>; 531 compatible = "fsl,imx7d-ocotp", "syscon"; 532 reg = <0x30350000 0x10000>; 533 clocks = <&clks IMX7D_OCOTP_CLK>; 534 535 tempmon_calib: calib@3c { 536 reg = <0x3c 0x4>; 537 }; 538 539 tempmon_temp_grade: temp-grade@10 { 540 reg = <0x10 0x4>; 541 }; 542 }; 543 544 tempmon: tempmon { 545 compatible = "fsl,imx7d-tempmon"; 546 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 547 fsl,tempmon =<&anatop>; 548 nvmem-cells = <&tempmon_calib>, 549 <&tempmon_temp_grade>; 550 nvmem-cell-names = "calib", "temp_grade"; 551 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 552 }; 553 554 anatop: anatop@30360000 { 555 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 556 "syscon", "simple-bus"; 557 reg = <0x30360000 0x10000>; 558 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 563 reg_1p0d: regulator-vdd1p0d@30360210 { 564 reg = <0x30360210>; 565 compatible = "fsl,anatop-regulator"; 566 regulator-name = "vdd1p0d"; 567 regulator-min-microvolt = <800000>; 568 regulator-max-microvolt = <1200000>; 569 anatop-reg-offset = <0x210>; 570 anatop-vol-bit-shift = <8>; 571 anatop-vol-bit-width = <5>; 572 anatop-min-bit-val = <8>; 573 anatop-min-voltage = <800000>; 574 anatop-max-voltage = <1200000>; 575 anatop-enable-bit = <0>; 576 }; 577 }; 578 579 snvs: snvs@30370000 { 580 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 581 reg = <0x30370000 0x10000>; 582 583 snvs_rtc: snvs-rtc-lp { 584 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 585 regmap = <&snvs>; 586 offset = <0x34>; 587 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&clks IMX7D_SNVS_CLK>; 590 clock-names = "snvs-rtc"; 591 }; 592 593 snvs_poweroff: snvs-poweroff { 594 compatible = "syscon-poweroff"; 595 regmap = <&snvs>; 596 offset = <0x38>; 597 value = <0x60>; 598 mask = <0x60>; 599 }; 600 601 snvs_pwrkey: snvs-powerkey { 602 compatible = "fsl,sec-v4.0-pwrkey"; 603 regmap = <&snvs>; 604 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 605 linux,keycode = <KEY_POWER>; 606 wakeup-source; 607 }; 608 }; 609 610 clks: ccm@30380000 { 611 compatible = "fsl,imx7d-ccm"; 612 reg = <0x30380000 0x10000>; 613 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 615 #clock-cells = <1>; 616 clocks = <&ckil>, <&osc>; 617 clock-names = "ckil", "osc"; 618 }; 619 620 src: src@30390000 { 621 compatible = "fsl,imx7d-src", "syscon"; 622 reg = <0x30390000 0x10000>; 623 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 624 #reset-cells = <1>; 625 }; 626 627 gpc: gpc@303a0000 { 628 compatible = "fsl,imx7d-gpc"; 629 reg = <0x303a0000 0x10000>; 630 interrupt-controller; 631 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 632 #interrupt-cells = <3>; 633 interrupt-parent = <&intc>; 634 #power-domain-cells = <1>; 635 636 pgc { 637 #address-cells = <1>; 638 #size-cells = <0>; 639 640 pgc_pcie_phy: pgc-power-domain@1 { 641 #power-domain-cells = <0>; 642 reg = <1>; 643 power-supply = <®_1p0d>; 644 }; 645 }; 646 }; 647 }; 648 649 aips2: aips-bus@30400000 { 650 compatible = "fsl,aips-bus", "simple-bus"; 651 #address-cells = <1>; 652 #size-cells = <1>; 653 reg = <0x30400000 0x400000>; 654 ranges; 655 656 adc1: adc@30610000 { 657 compatible = "fsl,imx7d-adc"; 658 reg = <0x30610000 0x10000>; 659 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 661 clock-names = "adc"; 662 status = "disabled"; 663 }; 664 665 adc2: adc@30620000 { 666 compatible = "fsl,imx7d-adc"; 667 reg = <0x30620000 0x10000>; 668 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 670 clock-names = "adc"; 671 status = "disabled"; 672 }; 673 674 ecspi4: ecspi@30630000 { 675 #address-cells = <1>; 676 #size-cells = <0>; 677 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 678 reg = <0x30630000 0x10000>; 679 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 681 <&clks IMX7D_ECSPI4_ROOT_CLK>; 682 clock-names = "ipg", "per"; 683 status = "disabled"; 684 }; 685 686 pwm1: pwm@30660000 { 687 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 688 reg = <0x30660000 0x10000>; 689 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 691 <&clks IMX7D_PWM1_ROOT_CLK>; 692 clock-names = "ipg", "per"; 693 #pwm-cells = <3>; 694 status = "disabled"; 695 }; 696 697 pwm2: pwm@30670000 { 698 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 699 reg = <0x30670000 0x10000>; 700 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 702 <&clks IMX7D_PWM2_ROOT_CLK>; 703 clock-names = "ipg", "per"; 704 #pwm-cells = <3>; 705 status = "disabled"; 706 }; 707 708 pwm3: pwm@30680000 { 709 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 710 reg = <0x30680000 0x10000>; 711 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 713 <&clks IMX7D_PWM3_ROOT_CLK>; 714 clock-names = "ipg", "per"; 715 #pwm-cells = <3>; 716 status = "disabled"; 717 }; 718 719 pwm4: pwm@30690000 { 720 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 721 reg = <0x30690000 0x10000>; 722 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 724 <&clks IMX7D_PWM4_ROOT_CLK>; 725 clock-names = "ipg", "per"; 726 #pwm-cells = <3>; 727 status = "disabled"; 728 }; 729 730 lcdif: lcdif@30730000 { 731 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; 732 reg = <0x30730000 0x10000>; 733 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 735 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 736 clock-names = "pix", "axi"; 737 status = "disabled"; 738 }; 739 }; 740 741 aips3: aips-bus@30800000 { 742 compatible = "fsl,aips-bus", "simple-bus"; 743 #address-cells = <1>; 744 #size-cells = <1>; 745 reg = <0x30800000 0x400000>; 746 ranges; 747 748 spba-bus@30800000 { 749 compatible = "fsl,spba-bus", "simple-bus"; 750 #address-cells = <1>; 751 #size-cells = <1>; 752 reg = <0x30800000 0x100000>; 753 ranges; 754 755 ecspi1: ecspi@30820000 { 756 #address-cells = <1>; 757 #size-cells = <0>; 758 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 759 reg = <0x30820000 0x10000>; 760 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 762 <&clks IMX7D_ECSPI1_ROOT_CLK>; 763 clock-names = "ipg", "per"; 764 status = "disabled"; 765 }; 766 767 ecspi2: ecspi@30830000 { 768 #address-cells = <1>; 769 #size-cells = <0>; 770 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 771 reg = <0x30830000 0x10000>; 772 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 774 <&clks IMX7D_ECSPI2_ROOT_CLK>; 775 clock-names = "ipg", "per"; 776 status = "disabled"; 777 }; 778 779 ecspi3: ecspi@30840000 { 780 #address-cells = <1>; 781 #size-cells = <0>; 782 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 783 reg = <0x30840000 0x10000>; 784 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 786 <&clks IMX7D_ECSPI3_ROOT_CLK>; 787 clock-names = "ipg", "per"; 788 status = "disabled"; 789 }; 790 791 uart1: serial@30860000 { 792 compatible = "fsl,imx7d-uart", 793 "fsl,imx6q-uart"; 794 reg = <0x30860000 0x10000>; 795 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 797 <&clks IMX7D_UART1_ROOT_CLK>; 798 clock-names = "ipg", "per"; 799 status = "disabled"; 800 }; 801 802 uart2: serial@30890000 { 803 compatible = "fsl,imx7d-uart", 804 "fsl,imx6q-uart"; 805 reg = <0x30890000 0x10000>; 806 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 808 <&clks IMX7D_UART2_ROOT_CLK>; 809 clock-names = "ipg", "per"; 810 status = "disabled"; 811 }; 812 813 uart3: serial@30880000 { 814 compatible = "fsl,imx7d-uart", 815 "fsl,imx6q-uart"; 816 reg = <0x30880000 0x10000>; 817 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 819 <&clks IMX7D_UART3_ROOT_CLK>; 820 clock-names = "ipg", "per"; 821 status = "disabled"; 822 }; 823 824 sai1: sai@308a0000 { 825 #sound-dai-cells = <0>; 826 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 827 reg = <0x308a0000 0x10000>; 828 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 830 <&clks IMX7D_SAI1_ROOT_CLK>, 831 <&clks IMX7D_CLK_DUMMY>, 832 <&clks IMX7D_CLK_DUMMY>; 833 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 834 dma-names = "rx", "tx"; 835 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 836 status = "disabled"; 837 }; 838 839 sai2: sai@308b0000 { 840 #sound-dai-cells = <0>; 841 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 842 reg = <0x308b0000 0x10000>; 843 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 845 <&clks IMX7D_SAI2_ROOT_CLK>, 846 <&clks IMX7D_CLK_DUMMY>, 847 <&clks IMX7D_CLK_DUMMY>; 848 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 849 dma-names = "rx", "tx"; 850 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 851 status = "disabled"; 852 }; 853 854 sai3: sai@308c0000 { 855 #sound-dai-cells = <0>; 856 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 857 reg = <0x308c0000 0x10000>; 858 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 860 <&clks IMX7D_SAI3_ROOT_CLK>, 861 <&clks IMX7D_CLK_DUMMY>, 862 <&clks IMX7D_CLK_DUMMY>; 863 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 864 dma-names = "rx", "tx"; 865 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 866 status = "disabled"; 867 }; 868 }; 869 870 crypto: caam@30900000 { 871 compatible = "fsl,sec-v4.0"; 872 #address-cells = <1>; 873 #size-cells = <1>; 874 reg = <0x30900000 0x40000>; 875 ranges = <0 0x30900000 0x40000>; 876 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&clks IMX7D_CAAM_CLK>, 878 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 879 clock-names = "ipg", "aclk"; 880 881 sec_jr0: jr0@1000 { 882 compatible = "fsl,sec-v4.0-job-ring"; 883 reg = <0x1000 0x1000>; 884 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 885 }; 886 887 sec_jr1: jr1@2000 { 888 compatible = "fsl,sec-v4.0-job-ring"; 889 reg = <0x2000 0x1000>; 890 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 891 }; 892 893 sec_jr2: jr1@3000 { 894 compatible = "fsl,sec-v4.0-job-ring"; 895 reg = <0x3000 0x1000>; 896 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 897 }; 898 }; 899 900 flexcan1: can@30a00000 { 901 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 902 reg = <0x30a00000 0x10000>; 903 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&clks IMX7D_CLK_DUMMY>, 905 <&clks IMX7D_CAN1_ROOT_CLK>; 906 clock-names = "ipg", "per"; 907 status = "disabled"; 908 }; 909 910 flexcan2: can@30a10000 { 911 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 912 reg = <0x30a10000 0x10000>; 913 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&clks IMX7D_CLK_DUMMY>, 915 <&clks IMX7D_CAN2_ROOT_CLK>; 916 clock-names = "ipg", "per"; 917 status = "disabled"; 918 }; 919 920 i2c1: i2c@30a20000 { 921 #address-cells = <1>; 922 #size-cells = <0>; 923 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 924 reg = <0x30a20000 0x10000>; 925 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 927 status = "disabled"; 928 }; 929 930 i2c2: i2c@30a30000 { 931 #address-cells = <1>; 932 #size-cells = <0>; 933 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 934 reg = <0x30a30000 0x10000>; 935 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 937 status = "disabled"; 938 }; 939 940 i2c3: i2c@30a40000 { 941 #address-cells = <1>; 942 #size-cells = <0>; 943 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 944 reg = <0x30a40000 0x10000>; 945 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 947 status = "disabled"; 948 }; 949 950 i2c4: i2c@30a50000 { 951 #address-cells = <1>; 952 #size-cells = <0>; 953 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 954 reg = <0x30a50000 0x10000>; 955 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 957 status = "disabled"; 958 }; 959 960 uart4: serial@30a60000 { 961 compatible = "fsl,imx7d-uart", 962 "fsl,imx6q-uart"; 963 reg = <0x30a60000 0x10000>; 964 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 966 <&clks IMX7D_UART4_ROOT_CLK>; 967 clock-names = "ipg", "per"; 968 status = "disabled"; 969 }; 970 971 uart5: serial@30a70000 { 972 compatible = "fsl,imx7d-uart", 973 "fsl,imx6q-uart"; 974 reg = <0x30a70000 0x10000>; 975 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 977 <&clks IMX7D_UART5_ROOT_CLK>; 978 clock-names = "ipg", "per"; 979 status = "disabled"; 980 }; 981 982 uart6: serial@30a80000 { 983 compatible = "fsl,imx7d-uart", 984 "fsl,imx6q-uart"; 985 reg = <0x30a80000 0x10000>; 986 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 988 <&clks IMX7D_UART6_ROOT_CLK>; 989 clock-names = "ipg", "per"; 990 status = "disabled"; 991 }; 992 993 uart7: serial@30a90000 { 994 compatible = "fsl,imx7d-uart", 995 "fsl,imx6q-uart"; 996 reg = <0x30a90000 0x10000>; 997 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 999 <&clks IMX7D_UART7_ROOT_CLK>; 1000 clock-names = "ipg", "per"; 1001 status = "disabled"; 1002 }; 1003 1004 usbotg1: usb@30b10000 { 1005 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1006 reg = <0x30b10000 0x200>; 1007 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1009 fsl,usbphy = <&usbphynop1>; 1010 fsl,usbmisc = <&usbmisc1 0>; 1011 phy-clkgate-delay-us = <400>; 1012 status = "disabled"; 1013 }; 1014 1015 usbh: usb@30b30000 { 1016 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1017 reg = <0x30b30000 0x200>; 1018 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1020 fsl,usbphy = <&usbphynop3>; 1021 fsl,usbmisc = <&usbmisc3 0>; 1022 phy_type = "hsic"; 1023 dr_mode = "host"; 1024 phy-clkgate-delay-us = <400>; 1025 status = "disabled"; 1026 }; 1027 1028 usbmisc1: usbmisc@30b10200 { 1029 #index-cells = <1>; 1030 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1031 reg = <0x30b10200 0x200>; 1032 }; 1033 1034 usbmisc3: usbmisc@30b30200 { 1035 #index-cells = <1>; 1036 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1037 reg = <0x30b30200 0x200>; 1038 }; 1039 1040 usdhc1: usdhc@30b40000 { 1041 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1042 reg = <0x30b40000 0x10000>; 1043 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1045 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1046 <&clks IMX7D_USDHC1_ROOT_CLK>; 1047 clock-names = "ipg", "ahb", "per"; 1048 bus-width = <4>; 1049 status = "disabled"; 1050 }; 1051 1052 usdhc2: usdhc@30b50000 { 1053 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1054 reg = <0x30b50000 0x10000>; 1055 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1056 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1057 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1058 <&clks IMX7D_USDHC2_ROOT_CLK>; 1059 clock-names = "ipg", "ahb", "per"; 1060 bus-width = <4>; 1061 status = "disabled"; 1062 }; 1063 1064 usdhc3: usdhc@30b60000 { 1065 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1066 reg = <0x30b60000 0x10000>; 1067 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1069 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1070 <&clks IMX7D_USDHC3_ROOT_CLK>; 1071 clock-names = "ipg", "ahb", "per"; 1072 bus-width = <4>; 1073 status = "disabled"; 1074 }; 1075 1076 qspi1: qspi@30bb0000 { 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 compatible = "fsl,imx7d-qspi"; 1080 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; 1081 reg-names = "QuadSPI", "QuadSPI-memory"; 1082 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&clks IMX7D_QSPI_ROOT_CLK>, 1084 <&clks IMX7D_QSPI_ROOT_CLK>; 1085 clock-names = "qspi_en", "qspi"; 1086 status = "disabled"; 1087 }; 1088 1089 sdma: sdma@30bd0000 { 1090 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 1091 reg = <0x30bd0000 0x10000>; 1092 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&clks IMX7D_SDMA_CORE_CLK>, 1094 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 1095 clock-names = "ipg", "ahb"; 1096 #dma-cells = <3>; 1097 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1098 }; 1099 1100 fec1: ethernet@30be0000 { 1101 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 1102 reg = <0x30be0000 0x10000>; 1103 interrupt-names = "int0", "int1", "int2", "pps"; 1104 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1109 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1110 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1111 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1112 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 1113 clock-names = "ipg", "ahb", "ptp", 1114 "enet_clk_ref", "enet_out"; 1115 fsl,num-tx-queues=<3>; 1116 fsl,num-rx-queues=<3>; 1117 status = "disabled"; 1118 }; 1119 }; 1120 1121 dma_apbh: dma-apbh@33000000 { 1122 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1123 reg = <0x33000000 0x2000>; 1124 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1128 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1129 #dma-cells = <1>; 1130 dma-channels = <4>; 1131 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1132 }; 1133 1134 gpmi: gpmi-nand@33002000{ 1135 compatible = "fsl,imx7d-gpmi-nand"; 1136 #address-cells = <1>; 1137 #size-cells = <1>; 1138 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1139 reg-names = "gpmi-nand", "bch"; 1140 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1141 interrupt-names = "bch"; 1142 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, 1143 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1144 clock-names = "gpmi_io", "gpmi_bch_apb"; 1145 dmas = <&dma_apbh 0>; 1146 dma-names = "rx-tx"; 1147 status = "disabled"; 1148 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; 1149 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; 1150 }; 1151 }; 1152}; 1153