1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 NXP Semiconductors. 4 * Author: Fabio Estevam <fabio.estevam@nxp.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/input/input.h> 10#include "imx7s.dtsi" 11 12/ { 13 model = "Warp i.MX7 Board"; 14 compatible = "warp,imx7s-warp", "fsl,imx7s"; 15 16 memory@80000000 { 17 reg = <0x80000000 0x20000000>; 18 }; 19 20 aliases { 21 mmc0 = &usdhc3; 22 }; 23 24 gpio-keys { 25 compatible = "gpio-keys"; 26 pinctrl-0 = <&pinctrl_gpio>; 27 autorepeat; 28 29 back { 30 label = "Back"; 31 gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 32 linux,code = <KEY_BACK>; 33 wakeup-source; 34 }; 35 }; 36 37 reg_brcm: regulator-brcm { 38 compatible = "regulator-fixed"; 39 enable-active-high; 40 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; 41 pinctrl-names = "default"; 42 pinctrl-0 = <&pinctrl_brcm_reg>; 43 regulator-name = "brcm_reg"; 44 regulator-min-microvolt = <3300000>; 45 regulator-max-microvolt = <3300000>; 46 startup-delay-us = <200000>; 47 }; 48 49 reg_bt: regulator-bt { 50 compatible = "regulator-fixed"; 51 pinctrl-names = "default"; 52 pinctrl-0 = <&pinctrl_bt_reg>; 53 enable-active-high; 54 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; 55 regulator-name = "bt_reg"; 56 regulator-min-microvolt = <3300000>; 57 regulator-max-microvolt = <3300000>; 58 regulator-always-on; 59 }; 60 61 sound { 62 compatible = "simple-audio-card"; 63 simple-audio-card,name = "imx7-sgtl5000"; 64 simple-audio-card,format = "i2s"; 65 simple-audio-card,bitclock-master = <&dailink_master>; 66 simple-audio-card,frame-master = <&dailink_master>; 67 simple-audio-card,cpu { 68 sound-dai = <&sai1>; 69 }; 70 71 dailink_master: simple-audio-card,codec { 72 sound-dai = <&codec>; 73 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; 74 }; 75 }; 76}; 77 78&clks { 79 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 80 assigned-clock-rates = <884736000>; 81}; 82 83&i2c1 { 84 pinctrl-names = "default"; 85 pinctrl-0 = <&pinctrl_i2c1>; 86 status = "okay"; 87 88 pmic: pfuze3000@8 { 89 compatible = "fsl,pfuze3000"; 90 reg = <0x08>; 91 92 regulators { 93 sw1a_reg: sw1a { 94 regulator-min-microvolt = <700000>; 95 regulator-max-microvolt = <1475000>; 96 regulator-boot-on; 97 regulator-always-on; 98 regulator-ramp-delay = <6250>; 99 }; 100 101 /* use sw1c_reg to align with pfuze100/pfuze200 */ 102 sw1c_reg: sw1b { 103 regulator-min-microvolt = <700000>; 104 regulator-max-microvolt = <1475000>; 105 regulator-boot-on; 106 regulator-always-on; 107 regulator-ramp-delay = <6250>; 108 }; 109 110 sw2_reg: sw2 { 111 regulator-min-microvolt = <1500000>; 112 regulator-max-microvolt = <1850000>; 113 regulator-boot-on; 114 regulator-always-on; 115 }; 116 117 sw3a_reg: sw3 { 118 regulator-min-microvolt = <900000>; 119 regulator-max-microvolt = <1650000>; 120 regulator-boot-on; 121 regulator-always-on; 122 }; 123 124 swbst_reg: swbst { 125 regulator-min-microvolt = <5000000>; 126 regulator-max-microvolt = <5150000>; 127 }; 128 129 snvs_reg: vsnvs { 130 regulator-min-microvolt = <1000000>; 131 regulator-max-microvolt = <3000000>; 132 regulator-boot-on; 133 regulator-always-on; 134 }; 135 136 vref_reg: vrefddr { 137 regulator-boot-on; 138 regulator-always-on; 139 }; 140 141 vgen1_reg: vldo1 { 142 regulator-min-microvolt = <1800000>; 143 regulator-max-microvolt = <3300000>; 144 regulator-always-on; 145 }; 146 147 vgen2_reg: vldo2 { 148 regulator-min-microvolt = <800000>; 149 regulator-max-microvolt = <1550000>; 150 }; 151 152 vgen3_reg: vccsd { 153 regulator-min-microvolt = <2850000>; 154 regulator-max-microvolt = <3300000>; 155 regulator-always-on; 156 }; 157 158 vgen4_reg: v33 { 159 regulator-min-microvolt = <2850000>; 160 regulator-max-microvolt = <3300000>; 161 regulator-always-on; 162 }; 163 164 vgen5_reg: vldo3 { 165 regulator-min-microvolt = <1800000>; 166 regulator-max-microvolt = <3300000>; 167 regulator-always-on; 168 }; 169 170 vgen6_reg: vldo4 { 171 regulator-min-microvolt = <1800000>; 172 regulator-max-microvolt = <3300000>; 173 regulator-always-on; 174 }; 175 }; 176 }; 177}; 178 179&i2c2 { 180 clock-frequency = <100000>; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&pinctrl_i2c2>; 183 status = "okay"; 184}; 185 186&i2c3 { 187 clock-frequency = <100000>; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_i2c3>; 190 status = "okay"; 191}; 192 193&i2c4 { 194 clock-frequency = <100000>; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_i2c4>; 197 status = "okay"; 198 199 codec: sgtl5000@a { 200 #sound-dai-cells = <0>; 201 reg = <0x0a>; 202 compatible = "fsl,sgtl5000"; 203 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_sai1_mclk>; 206 VDDA-supply = <&vgen4_reg>; 207 VDDIO-supply = <&vgen4_reg>; 208 VDDD-supply = <&vgen2_reg>; 209 }; 210 211 mpl3115@60 { 212 compatible = "fsl,mpl3115"; 213 reg = <0x60>; 214 }; 215}; 216 217&sai1 { 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_sai1>; 220 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, 221 <&clks IMX7D_SAI1_ROOT_CLK>; 222 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 223 assigned-clock-rates = <0>, <36864000>; 224 status = "okay"; 225}; 226 227&uart1 { 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_uart1>; 230 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; 231 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 232 status = "okay"; 233}; 234 235&uart3 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_uart3>; 238 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; 239 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 240 uart-has-rtscts; 241 status = "okay"; 242}; 243 244&uart6 { 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_uart6>; 247 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 248 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 249 fsl,dte-mode; 250 status = "okay"; 251}; 252 253&usbotg1 { 254 dr_mode = "peripheral"; 255 status = "okay"; 256}; 257 258&usdhc1 { 259 pinctrl-names = "default"; 260 pinctrl-0 = <&pinctrl_usdhc1>; 261 bus-width = <4>; 262 keep-power-in-suspend; 263 no-1-8-v; 264 non-removable; 265 vmmc-supply = <®_brcm>; 266 status = "okay"; 267}; 268 269&usdhc3 { 270 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 271 pinctrl-0 = <&pinctrl_usdhc3>; 272 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 273 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 274 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; 275 assigned-clock-rates = <400000000>; 276 bus-width = <8>; 277 no-1-8-v; 278 fsl,tuning-step = <2>; 279 non-removable; 280 status = "okay"; 281}; 282 283&wdog1 { 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_wdog>; 286 fsl,ext-reset-output; 287 status = "okay"; 288}; 289 290&iomuxc { 291 pinctrl_brcm_reg: brcmreggrp { 292 fsl,pins = < 293 MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */ 294 >; 295 }; 296 297 pinctrl_bt_reg: btreggrp { 298 fsl,pins = < 299 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */ 300 >; 301 }; 302 303 pinctrl_gpio: gpiogrp { 304 fsl,pins = < 305 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14 306 >; 307 }; 308 309 pinctrl_i2c1: i2c1grp { 310 fsl,pins = < 311 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 312 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 313 >; 314 }; 315 316 pinctrl_i2c2: i2c2grp { 317 fsl,pins = < 318 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 319 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 320 >; 321 }; 322 323 pinctrl_i2c3: i2c3grp { 324 fsl,pins = < 325 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 326 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 327 >; 328 }; 329 330 pinctrl_i2c4: i2c4grp { 331 fsl,pins = < 332 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f 333 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f 334 >; 335 }; 336 337 pinctrl_sai1: sai1grp { 338 fsl,pins = < 339 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f 340 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f 341 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f 342 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 343 >; 344 }; 345 346 pinctrl_sai1_mclk: sai1mclkgrp { 347 fsl,pins = < 348 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f 349 >; 350 }; 351 352 pinctrl_uart1: uart1grp { 353 fsl,pins = < 354 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 355 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 356 >; 357 }; 358 359 pinctrl_uart3: uart3grp { 360 fsl,pins = < 361 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 362 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 363 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 364 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 365 >; 366 }; 367 368 pinctrl_uart6: uart6grp { 369 fsl,pins = < 370 MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79 371 MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79 372 >; 373 }; 374 375 pinctrl_usdhc1: usdhc1grp { 376 fsl,pins = < 377 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 378 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 379 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 380 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 381 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 382 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 383 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */ 384 >; 385 }; 386 387 pinctrl_usdhc3: usdhc3grp { 388 fsl,pins = < 389 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 390 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 391 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 392 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 393 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 394 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 395 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 396 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 397 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 398 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 399 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19 400 >; 401 }; 402 403 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 404 fsl,pins = < 405 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a 406 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a 407 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a 408 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a 409 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a 410 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a 411 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a 412 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a 413 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a 414 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a 415 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a 416 >; 417 }; 418 419 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 420 fsl,pins = < 421 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b 422 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b 423 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b 424 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b 425 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b 426 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b 427 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b 428 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b 429 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b 430 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b 431 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b 432 >; 433 }; 434}; 435 436&iomuxc_lpsr { 437 pinctrl_wdog: wdoggrp { 438 fsl,pins = < 439 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 440 >; 441 }; 442}; 443