1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2017 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx7d.dtsi" 9 10/ { 11 model = "Freescale i.MX7 SabreSD Board"; 12 compatible = "fsl,imx7d-sdb", "fsl,imx7d"; 13 14 memory { 15 reg = <0x80000000 0x80000000>; 16 }; 17 18 spi4 { 19 compatible = "spi-gpio"; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_spi1>; 22 status = "okay"; 23 gpio-sck = <&gpio1 13 0>; 24 gpio-mosi = <&gpio1 9 0>; 25 cs-gpios = <&gpio1 12 0>; 26 num-chipselects = <1>; 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 gpio_spi: gpio_spi@0 { 31 compatible = "fairchild,74hc595"; 32 gpio-controller; 33 #gpio-cells = <2>; 34 reg = <0>; 35 registers-number = <1>; 36 registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ 37 spi-max-frequency = <100000>; 38 }; 39 }; 40 41 regulators { 42 compatible = "simple-bus"; 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 reg_usb_otg1_vbus: regulator@0 { 47 compatible = "regulator-fixed"; 48 reg = <0>; 49 regulator-name = "usb_otg1_vbus"; 50 regulator-min-microvolt = <5000000>; 51 regulator-max-microvolt = <5000000>; 52 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 53 enable-active-high; 54 }; 55 56 reg_usb_otg2_vbus: regulator@1 { 57 compatible = "regulator-fixed"; 58 reg = <1>; 59 regulator-name = "usb_otg2_vbus"; 60 regulator-min-microvolt = <5000000>; 61 regulator-max-microvolt = <5000000>; 62 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 63 enable-active-high; 64 }; 65 66 reg_sd1_vmmc: regulator@3 { 67 compatible = "regulator-fixed"; 68 regulator-name = "VDD_SD1"; 69 regulator-min-microvolt = <3300000>; 70 regulator-max-microvolt = <3300000>; 71 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; 72 startup-delay-us = <200000>; 73 enable-active-high; 74 }; 75 }; 76}; 77 78&iomuxc { 79 imx7d-sdb { 80 pinctrl_spi1: spi1grp { 81 fsl,pins = < 82 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 83 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 84 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 85 >; 86 }; 87 88 pinctrl_i2c1: i2c1grp { 89 fsl,pins = < 90 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 91 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 92 >; 93 }; 94 95 pinctrl_i2c2: i2c2grp { 96 fsl,pins = < 97 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 98 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 99 >; 100 }; 101 102 pinctrl_i2c3: i2c3grp { 103 fsl,pins = < 104 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 105 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 106 >; 107 }; 108 109 pinctrl_i2c4: i2c4grp { 110 fsl,pins = < 111 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f 112 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f 113 >; 114 }; 115 116 pinctrl_usdhc1_gpio: usdhc1_gpiogrp { 117 fsl,pins = < 118 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ 119 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ 120 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ 121 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ 122 >; 123 }; 124 125 pinctrl_usdhc1: usdhc1grp { 126 fsl,pins = < 127 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 128 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 129 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 130 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 131 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 132 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 133 >; 134 }; 135 136 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { 137 fsl,pins = < 138 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a 139 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a 140 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a 141 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a 142 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a 143 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a 144 >; 145 }; 146 147 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { 148 fsl,pins = < 149 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b 150 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b 151 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b 152 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b 153 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b 154 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b 155 >; 156 }; 157 158 pinctrl_usdhc2: usdhc2grp { 159 fsl,pins = < 160 MX7D_PAD_SD2_CMD__SD2_CMD 0x59 161 MX7D_PAD_SD2_CLK__SD2_CLK 0x19 162 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 163 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 164 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 165 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 166 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */ 167 MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ 168 >; 169 }; 170 171 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { 172 fsl,pins = < 173 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a 174 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a 175 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a 176 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a 177 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a 178 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a 179 >; 180 }; 181 182 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { 183 fsl,pins = < 184 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b 185 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b 186 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b 187 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b 188 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b 189 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b 190 >; 191 }; 192 193 pinctrl_usdhc3: usdhc3grp { 194 fsl,pins = < 195 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 196 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 197 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 198 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 199 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 200 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 201 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 202 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 203 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 204 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 205 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 206 >; 207 }; 208 209 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 210 fsl,pins = < 211 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a 212 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a 213 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a 214 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a 215 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a 216 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a 217 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a 218 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a 219 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a 220 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a 221 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a 222 >; 223 }; 224 225 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 226 fsl,pins = < 227 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b 228 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b 229 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b 230 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b 231 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b 232 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b 233 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b 234 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b 235 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b 236 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b 237 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b 238 >; 239 }; 240 }; 241}; 242 243&i2c1 { 244 clock-frequency = <100000>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_i2c1>; 247 status = "okay"; 248 249 pmic: pfuze3000@08 { 250 compatible = "fsl,pfuze3000"; 251 reg = <0x08>; 252 253 regulators { 254 sw1a_reg: sw1a { 255 regulator-min-microvolt = <700000>; 256 regulator-max-microvolt = <3300000>; 257 regulator-boot-on; 258 regulator-always-on; 259 regulator-ramp-delay = <6250>; 260 }; 261 262 /* use sw1c_reg to align with pfuze100/pfuze200 */ 263 sw1c_reg: sw1b { 264 regulator-min-microvolt = <700000>; 265 regulator-max-microvolt = <1475000>; 266 regulator-boot-on; 267 regulator-always-on; 268 regulator-ramp-delay = <6250>; 269 }; 270 271 sw2_reg: sw2 { 272 regulator-min-microvolt = <1500000>; 273 regulator-max-microvolt = <1850000>; 274 regulator-boot-on; 275 regulator-always-on; 276 }; 277 278 sw3a_reg: sw3 { 279 regulator-min-microvolt = <900000>; 280 regulator-max-microvolt = <1650000>; 281 regulator-boot-on; 282 regulator-always-on; 283 }; 284 285 swbst_reg: swbst { 286 regulator-min-microvolt = <5000000>; 287 regulator-max-microvolt = <5150000>; 288 }; 289 290 snvs_reg: vsnvs { 291 regulator-min-microvolt = <1000000>; 292 regulator-max-microvolt = <3000000>; 293 regulator-boot-on; 294 regulator-always-on; 295 }; 296 297 vref_reg: vrefddr { 298 regulator-boot-on; 299 regulator-always-on; 300 }; 301 302 vgen1_reg: vldo1 { 303 regulator-min-microvolt = <1800000>; 304 regulator-max-microvolt = <3300000>; 305 regulator-always-on; 306 }; 307 308 vgen2_reg: vldo2 { 309 regulator-min-microvolt = <800000>; 310 regulator-max-microvolt = <1550000>; 311 regulator-always-on; 312 }; 313 314 vgen3_reg: vccsd { 315 regulator-min-microvolt = <2850000>; 316 regulator-max-microvolt = <3300000>; 317 regulator-always-on; 318 }; 319 320 vgen4_reg: v33 { 321 regulator-min-microvolt = <2850000>; 322 regulator-max-microvolt = <3300000>; 323 regulator-always-on; 324 }; 325 326 vgen5_reg: vldo3 { 327 regulator-min-microvolt = <1800000>; 328 regulator-max-microvolt = <3300000>; 329 regulator-always-on; 330 }; 331 332 vgen6_reg: vldo4 { 333 regulator-min-microvolt = <1800000>; 334 regulator-max-microvolt = <3300000>; 335 regulator-always-on; 336 }; 337 }; 338 }; 339}; 340 341&i2c2 { 342 clock-frequency = <100000>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_i2c2>; 345 status = "okay"; 346}; 347 348&i2c3 { 349 clock-frequency = <100000>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&pinctrl_i2c3>; 352 status = "okay"; 353}; 354 355&i2c4 { 356 clock-frequency = <100000>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&pinctrl_i2c4>; 359 status = "okay"; 360}; 361 362&usdhc1 { 363 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 364 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; 365 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; 366 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; 367 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 368 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 369 vmmc-supply = <®_sd1_vmmc>; 370 fsl,tuning-start-tap = <20>; 371 fsl,tuning-step= <2>; 372 status = "okay"; 373}; 374 375&usdhc2 { 376 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 377 pinctrl-0 = <&pinctrl_usdhc2>; 378 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 379 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 380 non-removable; 381 fsl,tuning-start-tap = <20>; 382 fsl,tuning-step= <2>; 383 status = "okay"; 384}; 385 386&usdhc3 { 387 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 388 pinctrl-0 = <&pinctrl_usdhc3>; 389 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 390 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 391 bus-width = <8>; 392 non-removable; 393 fsl,tuning-start-tap = <20>; 394 fsl,tuning-step= <2>; 395 status = "okay"; 396}; 397