1*3b823350SYe Li// SPDX-License-Identifier: GPL-2.0+ 2*3b823350SYe Li/* 3*3b823350SYe Li * Copyright (C) 2015 Freescale Semiconductor, Inc. 4*3b823350SYe Li * Copyright 2018 NXP 5*3b823350SYe Li */ 6*3b823350SYe Li 7*3b823350SYe Li#include "imx7d-sdb.dts" 8*3b823350SYe Li 9*3b823350SYe Li/* disable epdc, conflict with qspi */ 10*3b823350SYe Li&epdc { 11*3b823350SYe Li status = "disabled"; 12*3b823350SYe Li}; 13*3b823350SYe Li 14*3b823350SYe Li&iomuxc { 15*3b823350SYe Li qspi1 { 16*3b823350SYe Li pinctrl_qspi1_1: qspi1grp_1 { 17*3b823350SYe Li fsl,pins = < 18*3b823350SYe Li MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 19*3b823350SYe Li MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 20*3b823350SYe Li MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 21*3b823350SYe Li MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 22*3b823350SYe Li MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 23*3b823350SYe Li MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 24*3b823350SYe Li >; 25*3b823350SYe Li }; 26*3b823350SYe Li }; 27*3b823350SYe Li}; 28*3b823350SYe Li 29*3b823350SYe Li&qspi1 { 30*3b823350SYe Li pinctrl-names = "default"; 31*3b823350SYe Li pinctrl-0 = <&pinctrl_qspi1_1>; 32*3b823350SYe Li status = "okay"; 33*3b823350SYe Li ddrsmp=<0>; 34*3b823350SYe Li 35*3b823350SYe Li flash0: mx25l51245g@0 { 36*3b823350SYe Li #address-cells = <1>; 37*3b823350SYe Li #size-cells = <1>; 38*3b823350SYe Li compatible = "macronix,mx25l51245g"; 39*3b823350SYe Li spi-max-frequency = <29000000>; 40*3b823350SYe Li /* take off one dummy cycle */ 41*3b823350SYe Li spi-nor,ddr-quad-read-dummy = <5>; 42*3b823350SYe Li reg = <0>; 43*3b823350SYe Li }; 44*3b823350SYe Li}; 45