1/* 2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/input/input.h> 12#include "imx6ull.dtsi" 13 14/ { 15 model = "Freescale i.MX6 ULL 14x14 EVK Board"; 16 compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; 17 18 chosen { 19 stdout-path = &uart1; 20 }; 21 22 memory { 23 reg = <0x80000000 0x20000000>; 24 }; 25 26 backlight { 27 compatible = "pwm-backlight"; 28 pwms = <&pwm1 0 5000000>; 29 brightness-levels = <0 4 8 16 32 64 128 255>; 30 default-brightness-level = <6>; 31 status = "okay"; 32 }; 33 34 regulators { 35 compatible = "simple-bus"; 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 reg_can_3v3: regulator@0 { 40 compatible = "regulator-fixed"; 41 reg = <0>; 42 regulator-name = "can-3v3"; 43 regulator-min-microvolt = <3300000>; 44 regulator-max-microvolt = <3300000>; 45 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 46 }; 47 48 reg_sd1_vmmc: regulator@1 { 49 compatible = "regulator-fixed"; 50 regulator-name = "VSD_3V3"; 51 regulator-min-microvolt = <3300000>; 52 regulator-max-microvolt = <3300000>; 53 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 54 enable-active-high; 55 }; 56 57 reg_gpio_dvfs: regulator-gpio { 58 compatible = "regulator-gpio"; 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pinctrl_dvfs>; 61 regulator-min-microvolt = <1300000>; 62 regulator-max-microvolt = <1400000>; 63 regulator-name = "gpio_dvfs"; 64 regulator-type = "voltage"; 65 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 66 states = <1300000 0x1 1400000 0x0>; 67 }; 68 }; 69 70 spi5 { 71 compatible = "spi-gpio"; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_spi4>; 74 status = "okay"; 75 gpio-sck = <&gpio5 11 0>; 76 gpio-mosi = <&gpio5 10 0>; 77 cs-gpios = <&gpio5 7 0>; 78 num-chipselects = <1>; 79 #address-cells = <1>; 80 #size-cells = <0>; 81 82 gpio_spi: gpio_spi@0 { 83 compatible = "fairchild,74hc595"; 84 gpio-controller; 85 oe-gpios = <&gpio5 8 0>; 86 #gpio-cells = <2>; 87 reg = <0>; 88 registers-number = <1>; 89 registers-default = /bits/ 8 <0x57>; 90 spi-max-frequency = <100000>; 91 }; 92 }; 93}; 94 95&cpu0 { 96 arm-supply = <®_arm>; 97 soc-supply = <®_soc>; 98 dc-supply = <®_gpio_dvfs>; 99}; 100 101&clks { 102 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 103 assigned-clock-rates = <786432000>; 104}; 105 106&fec1 { 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_enet1>; 109 phy-mode = "rmii"; 110 phy-handle = <ðphy0>; 111 status = "okay"; 112}; 113 114&fec2 { 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pinctrl_enet2>; 117 phy-mode = "rmii"; 118 phy-handle = <ðphy1>; 119 status = "okay"; 120 121 mdio { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 125 ethphy0: ethernet-phy@2 { 126 compatible = "ethernet-phy-ieee802.3-c22"; 127 reg = <2>; 128 }; 129 130 ethphy1: ethernet-phy@1 { 131 compatible = "ethernet-phy-ieee802.3-c22"; 132 reg = <1>; 133 }; 134 }; 135}; 136 137&gpc { 138 fsl,cpu_pupscr_sw2iso = <0x1>; 139 fsl,cpu_pupscr_sw = <0x0>; 140 fsl,cpu_pdnscr_iso2sw = <0x1>; 141 fsl,cpu_pdnscr_iso = <0x1>; 142 fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ 143}; 144 145&i2c1 { 146 clock-frequency = <100000>; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_i2c1>; 149 status = "okay"; 150 151 mag3110@0e { 152 compatible = "fsl,mag3110"; 153 reg = <0x0e>; 154 position = <2>; 155 }; 156 157 fxls8471@1e { 158 compatible = "fsl,fxls8471"; 159 reg = <0x1e>; 160 position = <0>; 161 interrupt-parent = <&gpio5>; 162 interrupts = <0 8>; 163 }; 164}; 165 166&i2c2 { 167 clock_frequency = <100000>; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_i2c2>; 170 status = "okay"; 171}; 172 173&iomuxc { 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_hog_1>; 176 imx6ul-evk { 177 pinctrl_hog_1: hoggrp-1 { 178 fsl,pins = < 179 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 180 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 181 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 182 >; 183 }; 184 185 pinctrl_csi1: csi1grp { 186 fsl,pins = < 187 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 188 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 189 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 190 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 191 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 192 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 193 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 194 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 195 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 196 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 197 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 198 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 199 >; 200 }; 201 202 pinctrl_enet1: enet1grp { 203 fsl,pins = < 204 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 205 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 206 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 207 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 208 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 209 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 210 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 211 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 212 >; 213 }; 214 215 pinctrl_enet2: enet2grp { 216 fsl,pins = < 217 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 218 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 219 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 220 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 221 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 222 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 223 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 224 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 225 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 226 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 227 >; 228 }; 229 230 pinctrl_flexcan1: flexcan1grp{ 231 fsl,pins = < 232 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 233 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 234 >; 235 }; 236 237 pinctrl_flexcan2: flexcan2grp{ 238 fsl,pins = < 239 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 240 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 241 >; 242 }; 243 244 pinctrl_i2c1: i2c1grp { 245 fsl,pins = < 246 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 247 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 248 >; 249 }; 250 251 pinctrl_i2c2: i2c2grp { 252 fsl,pins = < 253 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 254 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 255 >; 256 }; 257 258 pinctrl_lcdif_dat: lcdifdatgrp { 259 fsl,pins = < 260 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 261 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 262 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 263 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 264 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 265 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 266 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 267 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 268 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 269 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 270 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 271 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 272 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 273 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 274 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 275 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 276 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 277 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 278 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 279 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 280 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 281 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 282 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 283 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 284 >; 285 }; 286 287 pinctrl_lcdif_ctrl: lcdifctrlgrp { 288 fsl,pins = < 289 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 290 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 291 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 292 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 293 >; 294 }; 295 296 pinctrl_pwm1: pwm1grp { 297 fsl,pins = < 298 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 299 >; 300 }; 301 302 pinctrl_qspi: qspigrp { 303 fsl,pins = < 304 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 305 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 306 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 307 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 308 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 309 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 310 >; 311 }; 312 313 pinctrl_uart1: uart1grp { 314 fsl,pins = < 315 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 316 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 317 >; 318 }; 319 320 pinctrl_uart2: uart2grp { 321 fsl,pins = < 322 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 323 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 324 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 325 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 326 >; 327 }; 328 329 pinctrl_uart2dte: uart2dtegrp { 330 fsl,pins = < 331 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 332 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 333 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 334 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 335 >; 336 }; 337 338 pinctrl_usdhc1: usdhc1grp { 339 fsl,pins = < 340 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 341 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 342 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 343 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 344 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 345 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 346 >; 347 }; 348 349 pinctrl_usdhc2: usdhc2grp { 350 fsl,pins = < 351 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 352 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 353 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 354 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 355 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 356 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 357 >; 358 }; 359 360 pinctrl_wdog: wdoggrp { 361 fsl,pins = < 362 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 363 >; 364 }; 365 }; 366}; 367 368&iomuxc_snvs { 369 pinctrl-names = "default_snvs"; 370 pinctrl-0 = <&pinctrl_hog_2>; 371 imx6ul-evk { 372 pinctrl_hog_2: hoggrp-2 { 373 fsl,pins = < 374 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 375 >; 376 }; 377 378 pinctrl_dvfs: dvfsgrp { 379 fsl,pins = < 380 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 381 >; 382 }; 383 384 pinctrl_lcdif_reset: lcdifresetgrp { 385 fsl,pins = < 386 /* used for lcd reset */ 387 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 388 >; 389 }; 390 391 pinctrl_spi4: spi4grp { 392 fsl,pins = < 393 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 394 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 395 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 396 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 397 >; 398 }; 399 400 pinctrl_sai2_hp_det_b: sai2_hp_det_grp { 401 fsl,pins = < 402 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 403 >; 404 }; 405 }; 406}; 407 408 409&lcdif { 410 pinctrl-names = "default"; 411 pinctrl-0 = <&pinctrl_lcdif_dat 412 &pinctrl_lcdif_ctrl 413 &pinctrl_lcdif_reset>; 414 display = <&display0>; 415 status = "okay"; 416 417 display0: display { 418 bits-per-pixel = <16>; 419 bus-width = <24>; 420 421 display-timings { 422 native-mode = <&timing0>; 423 timing0: timing0 { 424 clock-frequency = <9200000>; 425 hactive = <480>; 426 vactive = <272>; 427 hfront-porch = <8>; 428 hback-porch = <4>; 429 hsync-len = <41>; 430 vback-porch = <2>; 431 vfront-porch = <4>; 432 vsync-len = <10>; 433 434 hsync-active = <0>; 435 vsync-active = <0>; 436 de-active = <1>; 437 pixelclk-active = <0>; 438 }; 439 }; 440 }; 441}; 442 443&pwm1 { 444 pinctrl-names = "default"; 445 pinctrl-0 = <&pinctrl_pwm1>; 446 status = "okay"; 447}; 448 449&qspi { 450 pinctrl-names = "default"; 451 pinctrl-0 = <&pinctrl_qspi>; 452 status = "okay"; 453 ddrsmp=<0>; 454 455 flash0: n25q256a@0 { 456 #address-cells = <1>; 457 #size-cells = <1>; 458 /* compatible = "micron,n25q256a"; */ 459 compatible = "spi-flash"; 460 spi-max-frequency = <29000000>; 461 spi-nor,ddr-quad-read-dummy = <6>; 462 reg = <0>; 463 }; 464}; 465 466&uart1 { 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_uart1>; 469 status = "okay"; 470}; 471 472&uart2 { 473 pinctrl-names = "default"; 474 pinctrl-0 = <&pinctrl_uart2>; 475 fsl,uart-has-rtscts; 476 /* for DTE mode, add below change */ 477 /* fsl,dte-mode; */ 478 /* pinctrl-0 = <&pinctrl_uart2dte>; */ 479 status = "okay"; 480}; 481 482&usbotg1 { 483 dr_mode = "otg"; 484 srp-disable; 485 hnp-disable; 486 adp-disable; 487 status = "okay"; 488}; 489 490&usbotg2 { 491 dr_mode = "host"; 492 disable-over-current; 493 status = "okay"; 494}; 495 496&usbphy1 { 497 tx-d-cal = <0x5>; 498}; 499 500&usbphy2 { 501 tx-d-cal = <0x5>; 502}; 503 504&usdhc1 { 505 pinctrl-names = "default"; 506 pinctrl-0 = <&pinctrl_usdhc1>; 507 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 508 keep-power-in-suspend; 509 enable-sdio-wakeup; 510 vmmc-supply = <®_sd1_vmmc>; 511 status = "okay"; 512}; 513 514&usdhc2 { 515 pinctrl-names = "default"; 516 pinctrl-0 = <&pinctrl_usdhc2>; 517 no-1-8-v; 518 non-removable; 519 keep-power-in-suspend; 520 enable-sdio-wakeup; 521 status = "okay"; 522}; 523 524&wdog1 { 525 pinctrl-names = "default"; 526 pinctrl-0 = <&pinctrl_wdog>; 527 fsl,wdog_b; 528}; 529