1/* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#include <dt-bindings/clock/imx6ul-clock.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include "imx6ul-pinfunc.h" 14#include "skeleton.dtsi" 15 16/ { 17 aliases { 18 ethernet0 = &fec1; 19 ethernet1 = &fec2; 20 gpio0 = &gpio1; 21 gpio1 = &gpio2; 22 gpio2 = &gpio3; 23 gpio3 = &gpio4; 24 gpio4 = &gpio5; 25 i2c0 = &i2c1; 26 i2c1 = &i2c2; 27 i2c2 = &i2c3; 28 i2c3 = &i2c4; 29 mmc0 = &usdhc1; 30 mmc1 = &usdhc2; 31 serial0 = &uart1; 32 serial1 = &uart2; 33 serial2 = &uart3; 34 serial3 = &uart4; 35 serial4 = &uart5; 36 serial5 = &uart6; 37 serial6 = &uart7; 38 serial7 = &uart8; 39 sai1 = &sai1; 40 sai2 = &sai2; 41 sai3 = &sai3; 42 spi0 = &qspi; 43 spi1 = &ecspi1; 44 spi2 = &ecspi2; 45 spi3 = &ecspi3; 46 spi4 = &ecspi4; 47 usbphy0 = &usbphy1; 48 usbphy1 = &usbphy2; 49 usb0 = &usbotg1; 50 usb1 = &usbotg2; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a7"; 59 device_type = "cpu"; 60 reg = <0>; 61 clock-latency = <61036>; /* two CLK32 periods */ 62 operating-points = < 63 /* kHz uV */ 64 528000 1175000 65 396000 1025000 66 198000 950000 67 >; 68 fsl,soc-operating-points = < 69 /* KHz uV */ 70 528000 1175000 71 396000 1175000 72 198000 1175000 73 >; 74 clocks = <&clks IMX6UL_CLK_ARM>, 75 <&clks IMX6UL_CLK_PLL2_BUS>, 76 <&clks IMX6UL_CLK_PLL2_PFD2>, 77 <&clks IMX6UL_CA7_SECONDARY_SEL>, 78 <&clks IMX6UL_CLK_STEP>, 79 <&clks IMX6UL_CLK_PLL1_SW>, 80 <&clks IMX6UL_CLK_PLL1_SYS>, 81 <&clks IMX6UL_PLL1_BYPASS>, 82 <&clks IMX6UL_CLK_PLL1>, 83 <&clks IMX6UL_PLL1_BYPASS_SRC>, 84 <&clks IMX6UL_CLK_OSC>; 85 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", 86 "secondary_sel", "step", "pll1_sw", 87 "pll1_sys", "pll1_bypass", "pll1", 88 "pll1_bypass_src", "osc"; 89 arm-supply = <®_arm>; 90 soc-supply = <®_soc>; 91 }; 92 }; 93 94 intc: interrupt-controller@00a01000 { 95 compatible = "arm,cortex-a7-gic"; 96 #interrupt-cells = <3>; 97 interrupt-controller; 98 reg = <0x00a01000 0x1000>, 99 <0x00a02000 0x1000>, 100 <0x00a04000 0x2000>, 101 <0x00a06000 0x2000>; 102 }; 103 104 ckil: clock-cli { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <32768>; 108 clock-output-names = "ckil"; 109 }; 110 111 osc: clock-osc { 112 compatible = "fixed-clock"; 113 #clock-cells = <0>; 114 clock-frequency = <24000000>; 115 clock-output-names = "osc"; 116 }; 117 118 ipp_di0: clock-di0 { 119 compatible = "fixed-clock"; 120 #clock-cells = <0>; 121 clock-frequency = <0>; 122 clock-output-names = "ipp_di0"; 123 }; 124 125 ipp_di1: clock-di1 { 126 compatible = "fixed-clock"; 127 #clock-cells = <0>; 128 clock-frequency = <0>; 129 clock-output-names = "ipp_di1"; 130 }; 131 132 soc { 133 #address-cells = <1>; 134 #size-cells = <1>; 135 compatible = "simple-bus"; 136 interrupt-parent = <&gpc>; 137 ranges; 138 139 pmu { 140 compatible = "arm,cortex-a7-pmu"; 141 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 142 status = "disabled"; 143 }; 144 145 ocram: sram@00900000 { 146 compatible = "mmio-sram"; 147 reg = <0x00900000 0x20000>; 148 }; 149 150 dma_apbh: dma-apbh@01804000 { 151 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 152 reg = <0x01804000 0x2000>; 153 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, 154 <0 13 IRQ_TYPE_LEVEL_HIGH>, 155 <0 13 IRQ_TYPE_LEVEL_HIGH>, 156 <0 13 IRQ_TYPE_LEVEL_HIGH>; 157 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 158 #dma-cells = <1>; 159 dma-channels = <4>; 160 clocks = <&clks IMX6UL_CLK_APBHDMA>; 161 }; 162 163 gpmi: gpmi-nand@01806000 { 164 compatible = "fsl,imx6q-gpmi-nand"; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 reg = <0x01806000 0x2000>, <0x01808000 0x2000>; 168 reg-names = "gpmi-nand", "bch"; 169 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 170 interrupt-names = "bch"; 171 clocks = <&clks IMX6UL_CLK_GPMI_IO>, 172 <&clks IMX6UL_CLK_GPMI_APB>, 173 <&clks IMX6UL_CLK_GPMI_BCH>, 174 <&clks IMX6UL_CLK_GPMI_BCH_APB>, 175 <&clks IMX6UL_CLK_PER_BCH>; 176 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 177 "gpmi_bch_apb", "per1_bch"; 178 dmas = <&dma_apbh 0>; 179 dma-names = "rx-tx"; 180 status = "disabled"; 181 }; 182 183 aips1: aips-bus@02000000 { 184 compatible = "fsl,aips-bus", "simple-bus"; 185 #address-cells = <1>; 186 #size-cells = <1>; 187 reg = <0x02000000 0x100000>; 188 ranges; 189 190 spba-bus@02000000 { 191 compatible = "fsl,spba-bus", "simple-bus"; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 reg = <0x02000000 0x40000>; 195 ranges; 196 u-boot,dm-spl; 197 198 ecspi1: ecspi@02008000 { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 202 reg = <0x02008000 0x4000>; 203 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&clks IMX6UL_CLK_ECSPI1>, 205 <&clks IMX6UL_CLK_ECSPI1>; 206 clock-names = "ipg", "per"; 207 status = "disabled"; 208 }; 209 210 ecspi2: ecspi@0200c000 { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 214 reg = <0x0200c000 0x4000>; 215 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&clks IMX6UL_CLK_ECSPI2>, 217 <&clks IMX6UL_CLK_ECSPI2>; 218 clock-names = "ipg", "per"; 219 status = "disabled"; 220 }; 221 222 ecspi3: ecspi@02010000 { 223 #address-cells = <1>; 224 #size-cells = <0>; 225 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 226 reg = <0x02010000 0x4000>; 227 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&clks IMX6UL_CLK_ECSPI3>, 229 <&clks IMX6UL_CLK_ECSPI3>; 230 clock-names = "ipg", "per"; 231 status = "disabled"; 232 }; 233 234 ecspi4: ecspi@02014000 { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 238 reg = <0x02014000 0x4000>; 239 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&clks IMX6UL_CLK_ECSPI4>, 241 <&clks IMX6UL_CLK_ECSPI4>; 242 clock-names = "ipg", "per"; 243 status = "disabled"; 244 }; 245 246 uart7: serial@02018000 { 247 compatible = "fsl,imx6ul-uart", 248 "fsl,imx6q-uart"; 249 reg = <0x02018000 0x4000>; 250 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&clks IMX6UL_CLK_UART7_IPG>, 252 <&clks IMX6UL_CLK_UART7_SERIAL>; 253 clock-names = "ipg", "per"; 254 status = "disabled"; 255 }; 256 257 uart1: serial@02020000 { 258 compatible = "fsl,imx6ul-uart", 259 "fsl,imx6q-uart"; 260 reg = <0x02020000 0x4000>; 261 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&clks IMX6UL_CLK_UART1_IPG>, 263 <&clks IMX6UL_CLK_UART1_SERIAL>; 264 clock-names = "ipg", "per"; 265 status = "disabled"; 266 }; 267 268 uart8: serial@02024000 { 269 compatible = "fsl,imx6ul-uart", 270 "fsl,imx6q-uart"; 271 reg = <0x02024000 0x4000>; 272 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&clks IMX6UL_CLK_UART8_IPG>, 274 <&clks IMX6UL_CLK_UART8_SERIAL>; 275 clock-names = "ipg", "per"; 276 status = "disabled"; 277 }; 278 279 sai1: sai@02028000 { 280 #sound-dai-cells = <0>; 281 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 282 reg = <0x02028000 0x4000>; 283 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&clks IMX6UL_CLK_SAI1_IPG>, 285 <&clks IMX6UL_CLK_SAI1>, 286 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 287 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 288 dmas = <&sdma 35 24 0>, 289 <&sdma 36 24 0>; 290 dma-names = "rx", "tx"; 291 status = "disabled"; 292 }; 293 294 sai2: sai@0202c000 { 295 #sound-dai-cells = <0>; 296 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 297 reg = <0x0202c000 0x4000>; 298 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&clks IMX6UL_CLK_SAI2_IPG>, 300 <&clks IMX6UL_CLK_SAI2>, 301 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 302 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 303 dmas = <&sdma 37 24 0>, 304 <&sdma 38 24 0>; 305 dma-names = "rx", "tx"; 306 status = "disabled"; 307 }; 308 309 sai3: sai@02030000 { 310 #sound-dai-cells = <0>; 311 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 312 reg = <0x02030000 0x4000>; 313 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&clks IMX6UL_CLK_SAI3_IPG>, 315 <&clks IMX6UL_CLK_SAI3>, 316 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 317 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 318 dmas = <&sdma 39 24 0>, 319 <&sdma 40 24 0>; 320 dma-names = "rx", "tx"; 321 status = "disabled"; 322 }; 323 }; 324 325 tsc: tsc@02040000 { 326 compatible = "fsl,imx6ul-tsc"; 327 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; 328 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&clks IMX6UL_CLK_IPG>, 331 <&clks IMX6UL_CLK_ADC2>; 332 clock-names = "tsc", "adc"; 333 status = "disabled"; 334 }; 335 336 pwm1: pwm@02080000 { 337 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 338 reg = <0x02080000 0x4000>; 339 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&clks IMX6UL_CLK_PWM1>, 341 <&clks IMX6UL_CLK_PWM1>; 342 clock-names = "ipg", "per"; 343 #pwm-cells = <2>; 344 status = "disabled"; 345 }; 346 347 pwm2: pwm@02084000 { 348 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 349 reg = <0x02084000 0x4000>; 350 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&clks IMX6UL_CLK_PWM2>, 352 <&clks IMX6UL_CLK_PWM2>; 353 clock-names = "ipg", "per"; 354 #pwm-cells = <2>; 355 status = "disabled"; 356 }; 357 358 pwm3: pwm@02088000 { 359 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 360 reg = <0x02088000 0x4000>; 361 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&clks IMX6UL_CLK_PWM3>, 363 <&clks IMX6UL_CLK_PWM3>; 364 clock-names = "ipg", "per"; 365 #pwm-cells = <2>; 366 status = "disabled"; 367 }; 368 369 pwm4: pwm@0208c000 { 370 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 371 reg = <0x0208c000 0x4000>; 372 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&clks IMX6UL_CLK_PWM4>, 374 <&clks IMX6UL_CLK_PWM4>; 375 clock-names = "ipg", "per"; 376 #pwm-cells = <2>; 377 status = "disabled"; 378 }; 379 380 can1: flexcan@02090000 { 381 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; 382 reg = <0x02090000 0x4000>; 383 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&clks IMX6UL_CLK_CAN1_IPG>, 385 <&clks IMX6UL_CLK_CAN1_SERIAL>; 386 clock-names = "ipg", "per"; 387 status = "disabled"; 388 }; 389 390 can2: flexcan@02094000 { 391 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; 392 reg = <0x02094000 0x4000>; 393 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&clks IMX6UL_CLK_CAN2_IPG>, 395 <&clks IMX6UL_CLK_CAN2_SERIAL>; 396 clock-names = "ipg", "per"; 397 status = "disabled"; 398 }; 399 400 gpt1: gpt@02098000 { 401 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; 402 reg = <0x02098000 0x4000>; 403 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&clks IMX6UL_CLK_GPT1_BUS>, 405 <&clks IMX6UL_CLK_GPT1_SERIAL>; 406 clock-names = "ipg", "per"; 407 }; 408 409 gpio1: gpio@0209c000 { 410 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 411 reg = <0x0209c000 0x4000>; 412 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 414 gpio-controller; 415 #gpio-cells = <2>; 416 interrupt-controller; 417 #interrupt-cells = <2>; 418 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, 419 <&iomuxc 16 33 16>; 420 }; 421 422 gpio2: gpio@020a0000 { 423 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 424 reg = <0x020a0000 0x4000>; 425 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 427 gpio-controller; 428 #gpio-cells = <2>; 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; 432 }; 433 434 gpio3: gpio@020a4000 { 435 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 436 reg = <0x020a4000 0x4000>; 437 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 439 gpio-controller; 440 #gpio-cells = <2>; 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 gpio-ranges = <&iomuxc 0 65 29>; 444 }; 445 446 gpio4: gpio@020a8000 { 447 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 448 reg = <0x020a8000 0x4000>; 449 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 451 gpio-controller; 452 #gpio-cells = <2>; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; 456 }; 457 458 gpio5: gpio@020ac000 { 459 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 460 reg = <0x020ac000 0x4000>; 461 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 463 gpio-controller; 464 #gpio-cells = <2>; 465 interrupt-controller; 466 #interrupt-cells = <2>; 467 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; 468 }; 469 470 fec2: ethernet@020b4000 { 471 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; 472 reg = <0x020b4000 0x4000>; 473 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&clks IMX6UL_CLK_ENET>, 476 <&clks IMX6UL_CLK_ENET_AHB>, 477 <&clks IMX6UL_CLK_ENET_PTP>, 478 <&clks IMX6UL_CLK_ENET2_REF_125M>, 479 <&clks IMX6UL_CLK_ENET2_REF_125M>; 480 clock-names = "ipg", "ahb", "ptp", 481 "enet_clk_ref", "enet_out"; 482 fsl,num-tx-queues=<1>; 483 fsl,num-rx-queues=<1>; 484 status = "disabled"; 485 }; 486 487 kpp: kpp@020b8000 { 488 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; 489 reg = <0x020b8000 0x4000>; 490 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&clks IMX6UL_CLK_KPP>; 492 status = "disabled"; 493 }; 494 495 wdog1: wdog@020bc000 { 496 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 497 reg = <0x020bc000 0x4000>; 498 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&clks IMX6UL_CLK_WDOG1>; 500 }; 501 502 wdog2: wdog@020c0000 { 503 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 504 reg = <0x020c0000 0x4000>; 505 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&clks IMX6UL_CLK_WDOG2>; 507 status = "disabled"; 508 }; 509 510 clks: ccm@020c4000 { 511 compatible = "fsl,imx6ul-ccm"; 512 reg = <0x020c4000 0x4000>; 513 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 515 #clock-cells = <1>; 516 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; 517 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; 518 }; 519 520 anatop: anatop@020c8000 { 521 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", 522 "syscon", "simple-bus"; 523 reg = <0x020c8000 0x1000>; 524 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 527 528 reg_3p0: regulator-3p0 { 529 compatible = "fsl,anatop-regulator"; 530 regulator-name = "vdd3p0"; 531 regulator-min-microvolt = <2625000>; 532 regulator-max-microvolt = <3400000>; 533 anatop-reg-offset = <0x120>; 534 anatop-vol-bit-shift = <8>; 535 anatop-vol-bit-width = <5>; 536 anatop-min-bit-val = <0>; 537 anatop-min-voltage = <2625000>; 538 anatop-max-voltage = <3400000>; 539 anatop-enable-bit = <0>; 540 }; 541 542 reg_arm: regulator-vddcore { 543 compatible = "fsl,anatop-regulator"; 544 regulator-name = "cpu"; 545 regulator-min-microvolt = <725000>; 546 regulator-max-microvolt = <1450000>; 547 regulator-always-on; 548 anatop-reg-offset = <0x140>; 549 anatop-vol-bit-shift = <0>; 550 anatop-vol-bit-width = <5>; 551 anatop-delay-reg-offset = <0x170>; 552 anatop-delay-bit-shift = <24>; 553 anatop-delay-bit-width = <2>; 554 anatop-min-bit-val = <1>; 555 anatop-min-voltage = <725000>; 556 anatop-max-voltage = <1450000>; 557 }; 558 559 reg_soc: regulator-vddsoc { 560 compatible = "fsl,anatop-regulator"; 561 regulator-name = "vddsoc"; 562 regulator-min-microvolt = <725000>; 563 regulator-max-microvolt = <1450000>; 564 regulator-always-on; 565 anatop-reg-offset = <0x140>; 566 anatop-vol-bit-shift = <18>; 567 anatop-vol-bit-width = <5>; 568 anatop-delay-reg-offset = <0x170>; 569 anatop-delay-bit-shift = <28>; 570 anatop-delay-bit-width = <2>; 571 anatop-min-bit-val = <1>; 572 anatop-min-voltage = <725000>; 573 anatop-max-voltage = <1450000>; 574 }; 575 }; 576 577 usbphy1: usbphy@020c9000 { 578 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 579 reg = <0x020c9000 0x1000>; 580 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&clks IMX6UL_CLK_USBPHY1>; 582 phy-3p0-supply = <®_3p0>; 583 fsl,anatop = <&anatop>; 584 }; 585 586 usbphy2: usbphy@020ca000 { 587 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 588 reg = <0x020ca000 0x1000>; 589 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&clks IMX6UL_CLK_USBPHY2>; 591 phy-3p0-supply = <®_3p0>; 592 fsl,anatop = <&anatop>; 593 }; 594 595 snvs: snvs@020cc000 { 596 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 597 reg = <0x020cc000 0x4000>; 598 599 snvs_rtc: snvs-rtc-lp { 600 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 601 regmap = <&snvs>; 602 offset = <0x34>; 603 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 605 }; 606 607 snvs_poweroff: snvs-poweroff { 608 compatible = "syscon-poweroff"; 609 regmap = <&snvs>; 610 offset = <0x38>; 611 mask = <0x60>; 612 status = "disabled"; 613 }; 614 615 snvs_pwrkey: snvs-powerkey { 616 compatible = "fsl,sec-v4.0-pwrkey"; 617 regmap = <&snvs>; 618 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 619 linux,keycode = <KEY_POWER>; 620 wakeup-source; 621 }; 622 }; 623 624 epit1: epit@020d0000 { 625 reg = <0x020d0000 0x4000>; 626 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 627 }; 628 629 epit2: epit@020d4000 { 630 reg = <0x020d4000 0x4000>; 631 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 632 }; 633 634 src: src@020d8000 { 635 compatible = "fsl,imx6ul-src", "fsl,imx51-src"; 636 reg = <0x020d8000 0x4000>; 637 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 639 #reset-cells = <1>; 640 }; 641 642 gpc: gpc@020dc000 { 643 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; 644 reg = <0x020dc000 0x4000>; 645 interrupt-controller; 646 #interrupt-cells = <3>; 647 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 648 interrupt-parent = <&intc>; 649 }; 650 651 iomuxc: iomuxc@020e0000 { 652 compatible = "fsl,imx6ul-iomuxc"; 653 reg = <0x020e0000 0x4000>; 654 }; 655 656 gpr: iomuxc-gpr@020e4000 { 657 compatible = "fsl,imx6ul-iomuxc-gpr", 658 "fsl,imx6q-iomuxc-gpr", "syscon"; 659 reg = <0x020e4000 0x4000>; 660 }; 661 662 gpt2: gpt@020e8000 { 663 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; 664 reg = <0x020e8000 0x4000>; 665 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&clks IMX6UL_CLK_GPT2_BUS>, 667 <&clks IMX6UL_CLK_GPT2_SERIAL>; 668 clock-names = "ipg", "per"; 669 }; 670 671 sdma: sdma@020ec000 { 672 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", 673 "fsl,imx35-sdma"; 674 reg = <0x020ec000 0x4000>; 675 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&clks IMX6UL_CLK_SDMA>, 677 <&clks IMX6UL_CLK_SDMA>; 678 clock-names = "ipg", "ahb"; 679 #dma-cells = <3>; 680 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 681 }; 682 683 pwm5: pwm@020f0000 { 684 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 685 reg = <0x020f0000 0x4000>; 686 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&clks IMX6UL_CLK_PWM5>, 688 <&clks IMX6UL_CLK_PWM5>; 689 clock-names = "ipg", "per"; 690 #pwm-cells = <2>; 691 status = "disabled"; 692 }; 693 694 pwm6: pwm@020f4000 { 695 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 696 reg = <0x020f4000 0x4000>; 697 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&clks IMX6UL_CLK_PWM6>, 699 <&clks IMX6UL_CLK_PWM6>; 700 clock-names = "ipg", "per"; 701 #pwm-cells = <2>; 702 status = "disabled"; 703 }; 704 705 pwm7: pwm@020f8000 { 706 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 707 reg = <0x020f8000 0x4000>; 708 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&clks IMX6UL_CLK_PWM7>, 710 <&clks IMX6UL_CLK_PWM7>; 711 clock-names = "ipg", "per"; 712 #pwm-cells = <2>; 713 status = "disabled"; 714 }; 715 716 pwm8: pwm@020fc000 { 717 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 718 reg = <0x020fc000 0x4000>; 719 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&clks IMX6UL_CLK_PWM8>, 721 <&clks IMX6UL_CLK_PWM8>; 722 clock-names = "ipg", "per"; 723 #pwm-cells = <2>; 724 status = "disabled"; 725 }; 726 }; 727 728 aips2: aips-bus@02100000 { 729 compatible = "fsl,aips-bus", "simple-bus"; 730 #address-cells = <1>; 731 #size-cells = <1>; 732 reg = <0x02100000 0x100000>; 733 ranges; 734 735 usbotg1: usb@02184000 { 736 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; 737 reg = <0x02184000 0x200>; 738 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&clks IMX6UL_CLK_USBOH3>; 740 fsl,usbphy = <&usbphy1>; 741 fsl,usbmisc = <&usbmisc 0>; 742 fsl,anatop = <&anatop>; 743 ahb-burst-config = <0x0>; 744 tx-burst-size-dword = <0x10>; 745 rx-burst-size-dword = <0x10>; 746 status = "disabled"; 747 }; 748 749 usbotg2: usb@02184200 { 750 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; 751 reg = <0x02184200 0x200>; 752 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&clks IMX6UL_CLK_USBOH3>; 754 fsl,usbphy = <&usbphy2>; 755 fsl,usbmisc = <&usbmisc 1>; 756 ahb-burst-config = <0x0>; 757 tx-burst-size-dword = <0x10>; 758 rx-burst-size-dword = <0x10>; 759 status = "disabled"; 760 }; 761 762 usbmisc: usbmisc@02184800 { 763 #index-cells = <1>; 764 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; 765 reg = <0x02184800 0x200>; 766 }; 767 768 fec1: ethernet@02188000 { 769 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; 770 reg = <0x02188000 0x4000>; 771 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&clks IMX6UL_CLK_ENET>, 774 <&clks IMX6UL_CLK_ENET_AHB>, 775 <&clks IMX6UL_CLK_ENET_PTP>, 776 <&clks IMX6UL_CLK_ENET_REF>, 777 <&clks IMX6UL_CLK_ENET_REF>; 778 clock-names = "ipg", "ahb", "ptp", 779 "enet_clk_ref", "enet_out"; 780 fsl,num-tx-queues=<1>; 781 fsl,num-rx-queues=<1>; 782 status = "disabled"; 783 }; 784 785 usdhc1: usdhc@02190000 { 786 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; 787 reg = <0x02190000 0x4000>; 788 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&clks IMX6UL_CLK_USDHC1>, 790 <&clks IMX6UL_CLK_USDHC1>, 791 <&clks IMX6UL_CLK_USDHC1>; 792 clock-names = "ipg", "ahb", "per"; 793 bus-width = <4>; 794 status = "disabled"; 795 }; 796 797 usdhc2: usdhc@02194000 { 798 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; 799 reg = <0x02194000 0x4000>; 800 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&clks IMX6UL_CLK_USDHC2>, 802 <&clks IMX6UL_CLK_USDHC2>, 803 <&clks IMX6UL_CLK_USDHC2>; 804 clock-names = "ipg", "ahb", "per"; 805 bus-width = <4>; 806 status = "disabled"; 807 }; 808 809 adc1: adc@02198000 { 810 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; 811 reg = <0x02198000 0x4000>; 812 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&clks IMX6UL_CLK_ADC1>; 814 num-channels = <2>; 815 clock-names = "adc"; 816 fsl,adck-max-frequency = <30000000>, <40000000>, 817 <20000000>; 818 status = "disabled"; 819 }; 820 821 i2c1: i2c@021a0000 { 822 #address-cells = <1>; 823 #size-cells = <0>; 824 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 825 reg = <0x021a0000 0x4000>; 826 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&clks IMX6UL_CLK_I2C1>; 828 status = "disabled"; 829 }; 830 831 i2c2: i2c@021a4000 { 832 #address-cells = <1>; 833 #size-cells = <0>; 834 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 835 reg = <0x021a4000 0x4000>; 836 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&clks IMX6UL_CLK_I2C2>; 838 status = "disabled"; 839 }; 840 841 i2c3: i2c@021a8000 { 842 #address-cells = <1>; 843 #size-cells = <0>; 844 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 845 reg = <0x021a8000 0x4000>; 846 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&clks IMX6UL_CLK_I2C3>; 848 status = "disabled"; 849 }; 850 851 mmdc: mmdc@021b0000 { 852 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; 853 reg = <0x021b0000 0x4000>; 854 }; 855 856 lcdif: lcdif@021c8000 { 857 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; 858 reg = <0x021c8000 0x4000>; 859 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, 861 <&clks IMX6UL_CLK_LCDIF_APB>, 862 <&clks IMX6UL_CLK_DUMMY>; 863 clock-names = "pix", "axi", "disp_axi"; 864 status = "disabled"; 865 }; 866 867 qspi: qspi@021e0000 { 868 #address-cells = <1>; 869 #size-cells = <0>; 870 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; 871 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 872 reg-names = "QuadSPI", "QuadSPI-memory"; 873 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&clks IMX6UL_CLK_QSPI>, 875 <&clks IMX6UL_CLK_QSPI>; 876 clock-names = "qspi_en", "qspi"; 877 status = "disabled"; 878 }; 879 880 wdog3: wdog@021e4000 { 881 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 882 reg = <0x021e4000 0x4000>; 883 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&clks IMX6UL_CLK_WDOG3>; 885 status = "disabled"; 886 }; 887 888 uart2: serial@021e8000 { 889 compatible = "fsl,imx6ul-uart", 890 "fsl,imx6q-uart"; 891 reg = <0x021e8000 0x4000>; 892 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&clks IMX6UL_CLK_UART2_IPG>, 894 <&clks IMX6UL_CLK_UART2_SERIAL>; 895 clock-names = "ipg", "per"; 896 status = "disabled"; 897 }; 898 899 uart3: serial@021ec000 { 900 compatible = "fsl,imx6ul-uart", 901 "fsl,imx6q-uart"; 902 reg = <0x021ec000 0x4000>; 903 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&clks IMX6UL_CLK_UART3_IPG>, 905 <&clks IMX6UL_CLK_UART3_SERIAL>; 906 clock-names = "ipg", "per"; 907 status = "disabled"; 908 }; 909 910 uart4: serial@021f0000 { 911 compatible = "fsl,imx6ul-uart", 912 "fsl,imx6q-uart"; 913 reg = <0x021f0000 0x4000>; 914 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&clks IMX6UL_CLK_UART4_IPG>, 916 <&clks IMX6UL_CLK_UART4_SERIAL>; 917 clock-names = "ipg", "per"; 918 status = "disabled"; 919 }; 920 921 uart5: serial@021f4000 { 922 compatible = "fsl,imx6ul-uart", 923 "fsl,imx6q-uart"; 924 reg = <0x021f4000 0x4000>; 925 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&clks IMX6UL_CLK_UART5_IPG>, 927 <&clks IMX6UL_CLK_UART5_SERIAL>; 928 clock-names = "ipg", "per"; 929 status = "disabled"; 930 }; 931 932 i2c4: i2c@021f8000 { 933 #address-cells = <1>; 934 #size-cells = <0>; 935 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 936 reg = <0x021f8000 0x4000>; 937 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&clks IMX6UL_CLK_I2C4>; 939 status = "disabled"; 940 }; 941 942 uart6: serial@021fc000 { 943 compatible = "fsl,imx6ul-uart", 944 "fsl,imx6q-uart"; 945 reg = <0x021fc000 0x4000>; 946 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&clks IMX6UL_CLK_UART6_IPG>, 948 <&clks IMX6UL_CLK_UART6_SERIAL>; 949 clock-names = "ipg", "per"; 950 status = "disabled"; 951 }; 952 }; 953 }; 954}; 955