1*e5c2244fSFabio Estevam// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*e5c2244fSFabio Estevam// 3*e5c2244fSFabio Estevam// Copyright 2015 Technexion Ltd. 4*e5c2244fSFabio Estevam// 5*e5c2244fSFabio Estevam// Author: Wig Cheng <wig.cheng@technexion.com> 6*e5c2244fSFabio Estevam// Richard Hu <richard.hu@technexion.com> 7*e5c2244fSFabio Estevam// Tapani Utriainen <tapani@technexion.com> 8*e5c2244fSFabio Estevam/dts-v1/; 9*e5c2244fSFabio Estevam 10*e5c2244fSFabio Estevam#include "imx6ul.dtsi" 11*e5c2244fSFabio Estevam 12*e5c2244fSFabio Estevam/ { 13*e5c2244fSFabio Estevam /* Will be filled by the bootloader */ 14*e5c2244fSFabio Estevam memory@80000000 { 15*e5c2244fSFabio Estevam device_type = "memory"; 16*e5c2244fSFabio Estevam reg = <0x80000000 0>; 17*e5c2244fSFabio Estevam }; 18*e5c2244fSFabio Estevam 19*e5c2244fSFabio Estevam chosen { 20*e5c2244fSFabio Estevam stdout-path = &uart6; 21*e5c2244fSFabio Estevam }; 22*e5c2244fSFabio Estevam 23*e5c2244fSFabio Estevam backlight { 24*e5c2244fSFabio Estevam compatible = "pwm-backlight"; 25*e5c2244fSFabio Estevam pwms = <&pwm3 0 5000000>; 26*e5c2244fSFabio Estevam brightness-levels = <0 4 8 16 32 64 128 255>; 27*e5c2244fSFabio Estevam default-brightness-level = <6>; 28*e5c2244fSFabio Estevam status = "okay"; 29*e5c2244fSFabio Estevam }; 30*e5c2244fSFabio Estevam 31*e5c2244fSFabio Estevam reg_2p5v: regulator-2p5v { 32*e5c2244fSFabio Estevam compatible = "regulator-fixed"; 33*e5c2244fSFabio Estevam regulator-name = "2P5V"; 34*e5c2244fSFabio Estevam regulator-min-microvolt = <2500000>; 35*e5c2244fSFabio Estevam regulator-max-microvolt = <2500000>; 36*e5c2244fSFabio Estevam }; 37*e5c2244fSFabio Estevam 38*e5c2244fSFabio Estevam reg_3p3v: regulator-3p3v { 39*e5c2244fSFabio Estevam compatible = "regulator-fixed"; 40*e5c2244fSFabio Estevam regulator-name = "3P3V"; 41*e5c2244fSFabio Estevam regulator-min-microvolt = <3300000>; 42*e5c2244fSFabio Estevam regulator-max-microvolt = <3300000>; 43*e5c2244fSFabio Estevam }; 44*e5c2244fSFabio Estevam 45*e5c2244fSFabio Estevam reg_sd1_vmmc: regulator-sd1-vmmc { 46*e5c2244fSFabio Estevam compatible = "regulator-fixed"; 47*e5c2244fSFabio Estevam regulator-name = "VSD_3V3"; 48*e5c2244fSFabio Estevam regulator-min-microvolt = <3300000>; 49*e5c2244fSFabio Estevam regulator-max-microvolt = <3300000>; 50*e5c2244fSFabio Estevam gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 51*e5c2244fSFabio Estevam enable-active-high; 52*e5c2244fSFabio Estevam }; 53*e5c2244fSFabio Estevam 54*e5c2244fSFabio Estevam reg_usb_otg_vbus: regulator-usb-otg-vbus { 55*e5c2244fSFabio Estevam compatible = "regulator-fixed"; 56*e5c2244fSFabio Estevam pinctrl-names = "default"; 57*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_usb_otg1>; 58*e5c2244fSFabio Estevam regulator-name = "usb_otg_vbus"; 59*e5c2244fSFabio Estevam regulator-min-microvolt = <5000000>; 60*e5c2244fSFabio Estevam regulator-max-microvolt = <5000000>; 61*e5c2244fSFabio Estevam gpio = <&gpio1 6 0>; 62*e5c2244fSFabio Estevam }; 63*e5c2244fSFabio Estevam 64*e5c2244fSFabio Estevam reg_brcm: regulator-brcm { 65*e5c2244fSFabio Estevam compatible = "regulator-fixed"; 66*e5c2244fSFabio Estevam enable-active-high; 67*e5c2244fSFabio Estevam gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; 68*e5c2244fSFabio Estevam pinctrl-names = "default"; 69*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_brcm_reg>; 70*e5c2244fSFabio Estevam regulator-name = "brcm_reg"; 71*e5c2244fSFabio Estevam regulator-min-microvolt = <3300000>; 72*e5c2244fSFabio Estevam regulator-max-microvolt = <3300000>; 73*e5c2244fSFabio Estevam startup-delay-us = <200000>; 74*e5c2244fSFabio Estevam }; 75*e5c2244fSFabio Estevam}; 76*e5c2244fSFabio Estevam 77*e5c2244fSFabio Estevam&can1 { 78*e5c2244fSFabio Estevam pinctrl-names = "default"; 79*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_flexcan1>; 80*e5c2244fSFabio Estevam status = "okay"; 81*e5c2244fSFabio Estevam}; 82*e5c2244fSFabio Estevam 83*e5c2244fSFabio Estevam&can2 { 84*e5c2244fSFabio Estevam pinctrl-names = "default"; 85*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_flexcan2>; 86*e5c2244fSFabio Estevam status = "okay"; 87*e5c2244fSFabio Estevam}; 88*e5c2244fSFabio Estevam 89*e5c2244fSFabio Estevam&clks { 90*e5c2244fSFabio Estevam assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 91*e5c2244fSFabio Estevam assigned-clock-rates = <786432000>; 92*e5c2244fSFabio Estevam}; 93*e5c2244fSFabio Estevam 94*e5c2244fSFabio Estevam&fec2 { 95*e5c2244fSFabio Estevam pinctrl-names = "default"; 96*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_enet2>; 97*e5c2244fSFabio Estevam phy-mode = "rmii"; 98*e5c2244fSFabio Estevam phy-handle = <ðphy1>; 99*e5c2244fSFabio Estevam status = "okay"; 100*e5c2244fSFabio Estevam phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; 101*e5c2244fSFabio Estevam phy-reset-duration = <1>; 102*e5c2244fSFabio Estevam 103*e5c2244fSFabio Estevam mdio { 104*e5c2244fSFabio Estevam #address-cells = <1>; 105*e5c2244fSFabio Estevam #size-cells = <0>; 106*e5c2244fSFabio Estevam 107*e5c2244fSFabio Estevam ethphy1: ethernet-phy@1 { 108*e5c2244fSFabio Estevam compatible = "ethernet-phy-ieee802.3-c22"; 109*e5c2244fSFabio Estevam reg = <1>; 110*e5c2244fSFabio Estevam max-speed = <100>; 111*e5c2244fSFabio Estevam interrupt-parent = <&gpio5>; 112*e5c2244fSFabio Estevam interrupts = <6 IRQ_TYPE_LEVEL_LOW>; 113*e5c2244fSFabio Estevam }; 114*e5c2244fSFabio Estevam }; 115*e5c2244fSFabio Estevam}; 116*e5c2244fSFabio Estevam 117*e5c2244fSFabio Estevam&i2c1 { 118*e5c2244fSFabio Estevam clock-frequency = <100000>; 119*e5c2244fSFabio Estevam pinctrl-names = "default"; 120*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_i2c1>; 121*e5c2244fSFabio Estevam status = "okay"; 122*e5c2244fSFabio Estevam 123*e5c2244fSFabio Estevam pmic: pfuze3000@8 { 124*e5c2244fSFabio Estevam compatible = "fsl,pfuze3000"; 125*e5c2244fSFabio Estevam reg = <0x08>; 126*e5c2244fSFabio Estevam 127*e5c2244fSFabio Estevam regulators { 128*e5c2244fSFabio Estevam /* VDD_ARM_SOC_IN*/ 129*e5c2244fSFabio Estevam sw1b_reg: sw1b { 130*e5c2244fSFabio Estevam regulator-min-microvolt = <700000>; 131*e5c2244fSFabio Estevam regulator-max-microvolt = <1475000>; 132*e5c2244fSFabio Estevam regulator-boot-on; 133*e5c2244fSFabio Estevam regulator-always-on; 134*e5c2244fSFabio Estevam regulator-ramp-delay = <6250>; 135*e5c2244fSFabio Estevam }; 136*e5c2244fSFabio Estevam 137*e5c2244fSFabio Estevam /* DRAM */ 138*e5c2244fSFabio Estevam sw3a_reg: sw3 { 139*e5c2244fSFabio Estevam regulator-min-microvolt = <900000>; 140*e5c2244fSFabio Estevam regulator-max-microvolt = <1650000>; 141*e5c2244fSFabio Estevam regulator-boot-on; 142*e5c2244fSFabio Estevam regulator-always-on; 143*e5c2244fSFabio Estevam }; 144*e5c2244fSFabio Estevam 145*e5c2244fSFabio Estevam /* DRAM */ 146*e5c2244fSFabio Estevam vref_reg: vrefddr { 147*e5c2244fSFabio Estevam regulator-boot-on; 148*e5c2244fSFabio Estevam regulator-always-on; 149*e5c2244fSFabio Estevam }; 150*e5c2244fSFabio Estevam }; 151*e5c2244fSFabio Estevam }; 152*e5c2244fSFabio Estevam}; 153*e5c2244fSFabio Estevam 154*e5c2244fSFabio Estevam&lcdif { 155*e5c2244fSFabio Estevam pinctrl-names = "default"; 156*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; 157*e5c2244fSFabio Estevam display = <&display0>; 158*e5c2244fSFabio Estevam status = "okay"; 159*e5c2244fSFabio Estevam 160*e5c2244fSFabio Estevam display0: display0 { 161*e5c2244fSFabio Estevam bits-per-pixel = <32>; 162*e5c2244fSFabio Estevam bus-width = <24>; 163*e5c2244fSFabio Estevam 164*e5c2244fSFabio Estevam display-timings { 165*e5c2244fSFabio Estevam native-mode = <&timing0>; 166*e5c2244fSFabio Estevam 167*e5c2244fSFabio Estevam timing0: timing0 { 168*e5c2244fSFabio Estevam clock-frequency = <33200000>; 169*e5c2244fSFabio Estevam hactive = <800>; 170*e5c2244fSFabio Estevam vactive = <480>; 171*e5c2244fSFabio Estevam hfront-porch = <210>; 172*e5c2244fSFabio Estevam hback-porch = <46>; 173*e5c2244fSFabio Estevam hsync-len = <1>; 174*e5c2244fSFabio Estevam vback-porch = <22>; 175*e5c2244fSFabio Estevam vfront-porch = <23>; 176*e5c2244fSFabio Estevam vsync-len = <1>; 177*e5c2244fSFabio Estevam hsync-active = <0>; 178*e5c2244fSFabio Estevam vsync-active = <0>; 179*e5c2244fSFabio Estevam de-active = <1>; 180*e5c2244fSFabio Estevam pixelclk-active = <0>; 181*e5c2244fSFabio Estevam }; 182*e5c2244fSFabio Estevam }; 183*e5c2244fSFabio Estevam }; 184*e5c2244fSFabio Estevam}; 185*e5c2244fSFabio Estevam 186*e5c2244fSFabio Estevam&pwm3 { 187*e5c2244fSFabio Estevam pinctrl-names = "default"; 188*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_pwm3>; 189*e5c2244fSFabio Estevam status = "okay"; 190*e5c2244fSFabio Estevam}; 191*e5c2244fSFabio Estevam 192*e5c2244fSFabio Estevam&pwm7 { 193*e5c2244fSFabio Estevam pinctrl-names = "default"; 194*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_pwm7>; 195*e5c2244fSFabio Estevam status = "okay"; 196*e5c2244fSFabio Estevam}; 197*e5c2244fSFabio Estevam 198*e5c2244fSFabio Estevam&pwm8 { 199*e5c2244fSFabio Estevam pinctrl-names = "default"; 200*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_pwm8>; 201*e5c2244fSFabio Estevam status = "okay"; 202*e5c2244fSFabio Estevam}; 203*e5c2244fSFabio Estevam 204*e5c2244fSFabio Estevam&sai1 { 205*e5c2244fSFabio Estevam pinctrl-names = "default"; 206*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_sai1>; 207*e5c2244fSFabio Estevam status = "okay"; 208*e5c2244fSFabio Estevam}; 209*e5c2244fSFabio Estevam 210*e5c2244fSFabio Estevam&uart3 { 211*e5c2244fSFabio Estevam pinctrl-names = "default"; 212*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_uart3>; 213*e5c2244fSFabio Estevam uart-has-rtscts; 214*e5c2244fSFabio Estevam status = "okay"; 215*e5c2244fSFabio Estevam}; 216*e5c2244fSFabio Estevam 217*e5c2244fSFabio Estevam&uart6 { 218*e5c2244fSFabio Estevam pinctrl-names = "default"; 219*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_uart6>; 220*e5c2244fSFabio Estevam status = "okay"; 221*e5c2244fSFabio Estevam}; 222*e5c2244fSFabio Estevam 223*e5c2244fSFabio Estevam&usbotg1 { 224*e5c2244fSFabio Estevam vbus-supply = <®_usb_otg_vbus>; 225*e5c2244fSFabio Estevam pinctrl-names = "default"; 226*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_usb_otg1_id>; 227*e5c2244fSFabio Estevam dr_mode = "otg"; 228*e5c2244fSFabio Estevam disable-over-current; 229*e5c2244fSFabio Estevam status = "okay"; 230*e5c2244fSFabio Estevam}; 231*e5c2244fSFabio Estevam 232*e5c2244fSFabio Estevam&usbotg2 { 233*e5c2244fSFabio Estevam dr_mode = "host"; 234*e5c2244fSFabio Estevam disable-over-current; 235*e5c2244fSFabio Estevam status = "okay"; 236*e5c2244fSFabio Estevam}; 237*e5c2244fSFabio Estevam 238*e5c2244fSFabio Estevam&usdhc1 { 239*e5c2244fSFabio Estevam pinctrl-names = "default"; 240*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_usdhc1>; 241*e5c2244fSFabio Estevam bus-width = <8>; 242*e5c2244fSFabio Estevam no-1-8-v; 243*e5c2244fSFabio Estevam non-removable; 244*e5c2244fSFabio Estevam keep-power-in-suspend; 245*e5c2244fSFabio Estevam status = "okay"; 246*e5c2244fSFabio Estevam}; 247*e5c2244fSFabio Estevam 248*e5c2244fSFabio Estevam&usdhc2 { /* Wifi SDIO */ 249*e5c2244fSFabio Estevam pinctrl-names = "default"; 250*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_usdhc2>; 251*e5c2244fSFabio Estevam no-1-8-v; 252*e5c2244fSFabio Estevam non-removable; 253*e5c2244fSFabio Estevam keep-power-in-suspend; 254*e5c2244fSFabio Estevam wakeup-source; 255*e5c2244fSFabio Estevam vmmc-supply = <®_brcm>; 256*e5c2244fSFabio Estevam status = "okay"; 257*e5c2244fSFabio Estevam}; 258*e5c2244fSFabio Estevam 259*e5c2244fSFabio Estevam&wdog1 { 260*e5c2244fSFabio Estevam pinctrl-names = "default"; 261*e5c2244fSFabio Estevam pinctrl-0 = <&pinctrl_wdog>; 262*e5c2244fSFabio Estevam fsl,ext-reset-output; 263*e5c2244fSFabio Estevam}; 264*e5c2244fSFabio Estevam 265*e5c2244fSFabio Estevam&iomuxc { 266*e5c2244fSFabio Estevam pinctrl_brcm_reg: brcmreggrp { 267*e5c2244fSFabio Estevam fsl,pins = < 268*e5c2244fSFabio Estevam MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */ 269*e5c2244fSFabio Estevam MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */ 270*e5c2244fSFabio Estevam >; 271*e5c2244fSFabio Estevam }; 272*e5c2244fSFabio Estevam 273*e5c2244fSFabio Estevam pinctrl_enet2: enet2grp { 274*e5c2244fSFabio Estevam fsl,pins = < 275*e5c2244fSFabio Estevam MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 276*e5c2244fSFabio Estevam MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0 277*e5c2244fSFabio Estevam MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 278*e5c2244fSFabio Estevam MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 279*e5c2244fSFabio Estevam MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 280*e5c2244fSFabio Estevam MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 281*e5c2244fSFabio Estevam MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 282*e5c2244fSFabio Estevam MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 283*e5c2244fSFabio Estevam MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 284*e5c2244fSFabio Estevam MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 285*e5c2244fSFabio Estevam MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800 286*e5c2244fSFabio Estevam MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79 287*e5c2244fSFabio Estevam >; 288*e5c2244fSFabio Estevam }; 289*e5c2244fSFabio Estevam 290*e5c2244fSFabio Estevam pinctrl_flexcan1: flexcan1grp { 291*e5c2244fSFabio Estevam fsl,pins = < 292*e5c2244fSFabio Estevam MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 293*e5c2244fSFabio Estevam MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 294*e5c2244fSFabio Estevam >; 295*e5c2244fSFabio Estevam }; 296*e5c2244fSFabio Estevam 297*e5c2244fSFabio Estevam pinctrl_flexcan2: flexcan2grp { 298*e5c2244fSFabio Estevam fsl,pins = < 299*e5c2244fSFabio Estevam MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 300*e5c2244fSFabio Estevam MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 301*e5c2244fSFabio Estevam >; 302*e5c2244fSFabio Estevam }; 303*e5c2244fSFabio Estevam 304*e5c2244fSFabio Estevam pinctrl_i2c1: i2c1grp { 305*e5c2244fSFabio Estevam fsl,pins = < 306*e5c2244fSFabio Estevam MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 307*e5c2244fSFabio Estevam MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 308*e5c2244fSFabio Estevam >; 309*e5c2244fSFabio Estevam }; 310*e5c2244fSFabio Estevam 311*e5c2244fSFabio Estevam pinctrl_i2c2: i2c2grp { 312*e5c2244fSFabio Estevam fsl,pins = < 313*e5c2244fSFabio Estevam MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 314*e5c2244fSFabio Estevam MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 315*e5c2244fSFabio Estevam >; 316*e5c2244fSFabio Estevam }; 317*e5c2244fSFabio Estevam 318*e5c2244fSFabio Estevam pinctrl_i2c3: i2c3grp { 319*e5c2244fSFabio Estevam fsl,pins = < 320*e5c2244fSFabio Estevam MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0 321*e5c2244fSFabio Estevam MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0 322*e5c2244fSFabio Estevam >; 323*e5c2244fSFabio Estevam }; 324*e5c2244fSFabio Estevam 325*e5c2244fSFabio Estevam pinctrl_lcdif_dat: lcdifdatgrp { 326*e5c2244fSFabio Estevam fsl,pins = < 327*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 328*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 329*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 330*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 331*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 332*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 333*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 334*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 335*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 336*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 337*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 338*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 339*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 340*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 341*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 342*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 343*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 344*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 345*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 346*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 347*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 348*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 349*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 350*e5c2244fSFabio Estevam MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 351*e5c2244fSFabio Estevam >; 352*e5c2244fSFabio Estevam }; 353*e5c2244fSFabio Estevam 354*e5c2244fSFabio Estevam pinctrl_lcdif_ctrl: lcdifctrlgrp { 355*e5c2244fSFabio Estevam fsl,pins = < 356*e5c2244fSFabio Estevam MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 357*e5c2244fSFabio Estevam MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 358*e5c2244fSFabio Estevam MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 359*e5c2244fSFabio Estevam MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 360*e5c2244fSFabio Estevam /* LCD reset */ 361*e5c2244fSFabio Estevam MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 362*e5c2244fSFabio Estevam >; 363*e5c2244fSFabio Estevam }; 364*e5c2244fSFabio Estevam 365*e5c2244fSFabio Estevam pinctrl_pwm3: pwm3grp { 366*e5c2244fSFabio Estevam fsl,pins = < 367*e5c2244fSFabio Estevam MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0 368*e5c2244fSFabio Estevam >; 369*e5c2244fSFabio Estevam }; 370*e5c2244fSFabio Estevam 371*e5c2244fSFabio Estevam pinctrl_pwm7: pwm7grp { 372*e5c2244fSFabio Estevam fsl,pins = < 373*e5c2244fSFabio Estevam MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0 374*e5c2244fSFabio Estevam >; 375*e5c2244fSFabio Estevam }; 376*e5c2244fSFabio Estevam 377*e5c2244fSFabio Estevam pinctrl_pwm8: pwm8grp { 378*e5c2244fSFabio Estevam fsl,pins = < 379*e5c2244fSFabio Estevam MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 380*e5c2244fSFabio Estevam >; 381*e5c2244fSFabio Estevam }; 382*e5c2244fSFabio Estevam 383*e5c2244fSFabio Estevam pinctrl_sai1: sai1grp { 384*e5c2244fSFabio Estevam fsl,pins = < 385*e5c2244fSFabio Estevam MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 386*e5c2244fSFabio Estevam MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 387*e5c2244fSFabio Estevam MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 388*e5c2244fSFabio Estevam MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 389*e5c2244fSFabio Estevam >; 390*e5c2244fSFabio Estevam }; 391*e5c2244fSFabio Estevam 392*e5c2244fSFabio Estevam pinctrl_uart3: uart3grp { 393*e5c2244fSFabio Estevam fsl,pins = < 394*e5c2244fSFabio Estevam MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0 395*e5c2244fSFabio Estevam MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0 396*e5c2244fSFabio Estevam MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0 397*e5c2244fSFabio Estevam MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0 398*e5c2244fSFabio Estevam >; 399*e5c2244fSFabio Estevam }; 400*e5c2244fSFabio Estevam 401*e5c2244fSFabio Estevam pinctrl_uart5: uart5grp { 402*e5c2244fSFabio Estevam fsl,pins = < 403*e5c2244fSFabio Estevam MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1 404*e5c2244fSFabio Estevam MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1 405*e5c2244fSFabio Estevam MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 406*e5c2244fSFabio Estevam MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 407*e5c2244fSFabio Estevam >; 408*e5c2244fSFabio Estevam }; 409*e5c2244fSFabio Estevam 410*e5c2244fSFabio Estevam pinctrl_uart6: uart6grp { 411*e5c2244fSFabio Estevam fsl,pins = < 412*e5c2244fSFabio Estevam MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 413*e5c2244fSFabio Estevam MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 414*e5c2244fSFabio Estevam >; 415*e5c2244fSFabio Estevam }; 416*e5c2244fSFabio Estevam 417*e5c2244fSFabio Estevam pinctrl_usb_otg1: usbotg1grp { 418*e5c2244fSFabio Estevam fsl,pins = < 419*e5c2244fSFabio Estevam MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0 420*e5c2244fSFabio Estevam >; 421*e5c2244fSFabio Estevam }; 422*e5c2244fSFabio Estevam 423*e5c2244fSFabio Estevam pinctrl_usb_otg1_id: usbotg1idgrp { 424*e5c2244fSFabio Estevam fsl,pins = < 425*e5c2244fSFabio Estevam MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 426*e5c2244fSFabio Estevam >; 427*e5c2244fSFabio Estevam }; 428*e5c2244fSFabio Estevam 429*e5c2244fSFabio Estevam pinctrl_usdhc1: usdhc1grp { 430*e5c2244fSFabio Estevam fsl,pins = < 431*e5c2244fSFabio Estevam MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 432*e5c2244fSFabio Estevam MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 433*e5c2244fSFabio Estevam MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 434*e5c2244fSFabio Estevam MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 435*e5c2244fSFabio Estevam MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 436*e5c2244fSFabio Estevam MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 437*e5c2244fSFabio Estevam MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 438*e5c2244fSFabio Estevam MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 439*e5c2244fSFabio Estevam MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 440*e5c2244fSFabio Estevam MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 441*e5c2244fSFabio Estevam MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 442*e5c2244fSFabio Estevam >; 443*e5c2244fSFabio Estevam }; 444*e5c2244fSFabio Estevam 445*e5c2244fSFabio Estevam pinctrl_usdhc2: usdhc2grp { 446*e5c2244fSFabio Estevam fsl,pins = < 447*e5c2244fSFabio Estevam MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 448*e5c2244fSFabio Estevam MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 449*e5c2244fSFabio Estevam MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 450*e5c2244fSFabio Estevam MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 451*e5c2244fSFabio Estevam MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 452*e5c2244fSFabio Estevam MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 453*e5c2244fSFabio Estevam >; 454*e5c2244fSFabio Estevam }; 455*e5c2244fSFabio Estevam 456*e5c2244fSFabio Estevam pinctrl_wdog: wdoggrp { 457*e5c2244fSFabio Estevam fsl,pins = < 458*e5c2244fSFabio Estevam MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 459*e5c2244fSFabio Estevam >; 460*e5c2244fSFabio Estevam }; 461*e5c2244fSFabio Estevam}; 462