1*0963060cSMartyn Welch// SPDX-License-Identifier: GPL-2.0+ 2*0963060cSMartyn Welch/* 3*0963060cSMartyn Welch * Copyright (C) 2018 Collabora Ltd. 4*0963060cSMartyn Welch * 5*0963060cSMartyn Welch * Based on dts[i] from Phytec barebox port: 6*0963060cSMartyn Welch * Copyright (C) 2016 PHYTEC Messtechnik GmbH 7*0963060cSMartyn Welch * Author: Christian Hemp <c.hemp@phytec.de> 8*0963060cSMartyn Welch * 9*0963060cSMartyn Welch * The code contained herein is licensed under the GNU General Public 10*0963060cSMartyn Welch * License. You may obtain a copy of the GNU General Public License 11*0963060cSMartyn Welch * Version 2 or later at the following locations: 12*0963060cSMartyn Welch * 13*0963060cSMartyn Welch * http://www.opensource.org/licenses/gpl-license.html 14*0963060cSMartyn Welch * http://www.gnu.org/copyleft/gpl.html 15*0963060cSMartyn Welch */ 16*0963060cSMartyn Welch 17*0963060cSMartyn Welch/dts-v1/; 18*0963060cSMartyn Welch 19*0963060cSMartyn Welch#include "imx6ul-pcl063.dtsi" 20*0963060cSMartyn Welch 21*0963060cSMartyn Welch/ { 22*0963060cSMartyn Welch model = "Phytec phyBOARD-i.MX6UL-Segin SBC"; 23*0963060cSMartyn Welch compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-pcl063", 24*0963060cSMartyn Welch "fsl,imx6ul"; 25*0963060cSMartyn Welch}; 26*0963060cSMartyn Welch 27*0963060cSMartyn Welch&i2c1 { 28*0963060cSMartyn Welch i2c_rtc: rtc@68 { 29*0963060cSMartyn Welch compatible = "microcrystal,rv4162"; 30*0963060cSMartyn Welch reg = <0x68>; 31*0963060cSMartyn Welch status = "okay"; 32*0963060cSMartyn Welch }; 33*0963060cSMartyn Welch}; 34*0963060cSMartyn Welch 35*0963060cSMartyn Welch&uart5 { 36*0963060cSMartyn Welch pinctrl-names = "default"; 37*0963060cSMartyn Welch pinctrl-0 = <&pinctrl_uart5>; 38*0963060cSMartyn Welch uart-has-rtscts; 39*0963060cSMartyn Welch status = "okay"; 40*0963060cSMartyn Welch}; 41*0963060cSMartyn Welch 42*0963060cSMartyn Welch&usbotg1 { 43*0963060cSMartyn Welch pinctrl-names = "default"; 44*0963060cSMartyn Welch pinctrl-0 = <&pinctrl_usb_otg1_id>; 45*0963060cSMartyn Welch dr_mode = "otg"; 46*0963060cSMartyn Welch srp-disable; 47*0963060cSMartyn Welch hnp-disable; 48*0963060cSMartyn Welch adp-disable; 49*0963060cSMartyn Welch status = "okay"; 50*0963060cSMartyn Welch}; 51*0963060cSMartyn Welch 52*0963060cSMartyn Welch&usbotg2 { 53*0963060cSMartyn Welch dr_mode = "host"; 54*0963060cSMartyn Welch disable-over-current; 55*0963060cSMartyn Welch status = "okay"; 56*0963060cSMartyn Welch}; 57*0963060cSMartyn Welch 58*0963060cSMartyn Welch&iomuxc { 59*0963060cSMartyn Welch pinctrl-names = "default"; 60*0963060cSMartyn Welch 61*0963060cSMartyn Welch pinctrl_uart5: uart5grp { 62*0963060cSMartyn Welch fsl,pins = < 63*0963060cSMartyn Welch MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 64*0963060cSMartyn Welch MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 65*0963060cSMartyn Welch MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 66*0963060cSMartyn Welch MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 67*0963060cSMartyn Welch >; 68*0963060cSMartyn Welch }; 69*0963060cSMartyn Welch 70*0963060cSMartyn Welch pinctrl_usb_otg1_id: usbotg1idgrp { 71*0963060cSMartyn Welch fsl,pins = < 72*0963060cSMartyn Welch MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 73*0963060cSMartyn Welch >; 74*0963060cSMartyn Welch }; 75*0963060cSMartyn Welch 76*0963060cSMartyn Welch}; 77