1*77f29293SSébastien Szymanski/*
2*77f29293SSébastien Szymanski * Copyright 2017 Armadeus Systems <support@armadeus.com>
3*77f29293SSébastien Szymanski *
4*77f29293SSébastien Szymanski * This file is dual-licensed: you can use it either under the terms
5*77f29293SSébastien Szymanski * of the GPL or the X11 license, at your option. Note that this dual
6*77f29293SSébastien Szymanski * licensing only applies to this file, and not this project as a
7*77f29293SSébastien Szymanski * whole.
8*77f29293SSébastien Szymanski *
9*77f29293SSébastien Szymanski *  a) This file is free software; you can redistribute it and/or
10*77f29293SSébastien Szymanski *     modify it under the terms of the GNU General Public License as
11*77f29293SSébastien Szymanski *     published by the Free Software Foundation; either version 2 of
12*77f29293SSébastien Szymanski *     the License, or (at your option) any later version.
13*77f29293SSébastien Szymanski *
14*77f29293SSébastien Szymanski *     This file is distributed in the hope that it will be useful,
15*77f29293SSébastien Szymanski *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16*77f29293SSébastien Szymanski *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17*77f29293SSébastien Szymanski *     GNU General Public License for more details.
18*77f29293SSébastien Szymanski *
19*77f29293SSébastien Szymanski *     You should have received a copy of the GNU General Public
20*77f29293SSébastien Szymanski *     License along with this file; if not, write to the Free
21*77f29293SSébastien Szymanski *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22*77f29293SSébastien Szymanski *     MA 02110-1301 USA
23*77f29293SSébastien Szymanski *
24*77f29293SSébastien Szymanski * Or, alternatively,
25*77f29293SSébastien Szymanski *
26*77f29293SSébastien Szymanski *  b) Permission is hereby granted, free of charge, to any person
27*77f29293SSébastien Szymanski *     obtaining a copy of this software and associated documentation
28*77f29293SSébastien Szymanski *     files (the "Software"), to deal in the Software without
29*77f29293SSébastien Szymanski *     restriction, including without limitation the rights to use,
30*77f29293SSébastien Szymanski *     copy, modify, merge, publish, distribute, sublicense, and/or
31*77f29293SSébastien Szymanski *     sell copies of the Software, and to permit persons to whom the
32*77f29293SSébastien Szymanski *     Software is furnished to do so, subject to the following
33*77f29293SSébastien Szymanski *     conditions:
34*77f29293SSébastien Szymanski *
35*77f29293SSébastien Szymanski *     The above copyright notice and this permission notice shall be
36*77f29293SSébastien Szymanski *     included in all copies or substantial portions of the Software.
37*77f29293SSébastien Szymanski *
38*77f29293SSébastien Szymanski *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39*77f29293SSébastien Szymanski *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40*77f29293SSébastien Szymanski *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41*77f29293SSébastien Szymanski *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42*77f29293SSébastien Szymanski *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43*77f29293SSébastien Szymanski *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44*77f29293SSébastien Szymanski *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45*77f29293SSébastien Szymanski *     OTHER DEALINGS IN THE SOFTWARE.
46*77f29293SSébastien Szymanski */
47*77f29293SSébastien Szymanski
48*77f29293SSébastien Szymanski/dts-v1/;
49*77f29293SSébastien Szymanski#include "imx6ul-opos6ul.dtsi"
50*77f29293SSébastien Szymanski
51*77f29293SSébastien Szymanski/ {
52*77f29293SSébastien Szymanski	model = "Armadeus Systems OPOS6UL SoM on OPOS6ULDev board";
53*77f29293SSébastien Szymanski	compatible = "armadeus,opos6uldev", "armadeus,opos6ul", "fsl,imx6ul";
54*77f29293SSébastien Szymanski
55*77f29293SSébastien Szymanski	chosen {
56*77f29293SSébastien Szymanski		stdout-path = &uart1;
57*77f29293SSébastien Szymanski	};
58*77f29293SSébastien Szymanski
59*77f29293SSébastien Szymanski	backlight {
60*77f29293SSébastien Szymanski		compatible = "pwm-backlight";
61*77f29293SSébastien Szymanski		pwms = <&pwm3 0 191000>;
62*77f29293SSébastien Szymanski		brightness-levels = <0 4 8 16 32 64 128 255>;
63*77f29293SSébastien Szymanski		default-brightness-level = <7>;
64*77f29293SSébastien Szymanski		power-supply = <&reg_5v>;
65*77f29293SSébastien Szymanski		status = "okay";
66*77f29293SSébastien Szymanski	};
67*77f29293SSébastien Szymanski
68*77f29293SSébastien Szymanski	gpio-keys {
69*77f29293SSébastien Szymanski		compatible = "gpio-keys";
70*77f29293SSébastien Szymanski		pinctrl-names = "default";
71*77f29293SSébastien Szymanski		pinctrl-0 = <&pinctrl_gpio_keys>;
72*77f29293SSébastien Szymanski
73*77f29293SSébastien Szymanski		user-button {
74*77f29293SSébastien Szymanski			label = "User button";
75*77f29293SSébastien Szymanski			gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
76*77f29293SSébastien Szymanski			linux,code = <BTN_MISC>;
77*77f29293SSébastien Szymanski			wakeup-source;
78*77f29293SSébastien Szymanski		};
79*77f29293SSébastien Szymanski	};
80*77f29293SSébastien Szymanski
81*77f29293SSébastien Szymanski	leds {
82*77f29293SSébastien Szymanski		compatible = "gpio-leds";
83*77f29293SSébastien Szymanski
84*77f29293SSébastien Szymanski		user-led {
85*77f29293SSébastien Szymanski			label = "User";
86*77f29293SSébastien Szymanski			pinctrl-names = "default";
87*77f29293SSébastien Szymanski			pinctrl-0 = <&pinctrl_led>;
88*77f29293SSébastien Szymanski			gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
89*77f29293SSébastien Szymanski			linux,default-trigger = "heartbeat";
90*77f29293SSébastien Szymanski		};
91*77f29293SSébastien Szymanski	};
92*77f29293SSébastien Szymanski
93*77f29293SSébastien Szymanski	onewire {
94*77f29293SSébastien Szymanski		compatible = "w1-gpio";
95*77f29293SSébastien Szymanski		pinctrl-names = "default";
96*77f29293SSébastien Szymanski		pinctrl-0 = <&pinctrl_w1>;
97*77f29293SSébastien Szymanski		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
98*77f29293SSébastien Szymanski	};
99*77f29293SSébastien Szymanski
100*77f29293SSébastien Szymanski	reg_5v: regulator-5v {
101*77f29293SSébastien Szymanski		compatible = "regulator-fixed";
102*77f29293SSébastien Szymanski		regulator-name = "5V";
103*77f29293SSébastien Szymanski		regulator-min-microvolt = <5000000>;
104*77f29293SSébastien Szymanski		regulator-max-microvolt = <5000000>;
105*77f29293SSébastien Szymanski	};
106*77f29293SSébastien Szymanski
107*77f29293SSébastien Szymanski	reg_usbotg1_vbus: regulator-usbotg1vbus {
108*77f29293SSébastien Szymanski		compatible = "regulator-fixed";
109*77f29293SSébastien Szymanski		regulator-name = "usbotg1vbus";
110*77f29293SSébastien Szymanski		regulator-min-microvolt = <5000000>;
111*77f29293SSébastien Szymanski		regulator-max-microvolt = <5000000>;
112*77f29293SSébastien Szymanski		pinctrl-names = "default";
113*77f29293SSébastien Szymanski		pinctrl-0 = <&pinctrl_usbotg1_vbus>;
114*77f29293SSébastien Szymanski		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
115*77f29293SSébastien Szymanski		enable-active-high;
116*77f29293SSébastien Szymanski	};
117*77f29293SSébastien Szymanski
118*77f29293SSébastien Szymanski	reg_usbotg2_vbus: regulator-usbotg2vbus {
119*77f29293SSébastien Szymanski		compatible = "regulator-fixed";
120*77f29293SSébastien Szymanski		regulator-name = "usbotg2vbus";
121*77f29293SSébastien Szymanski		regulator-min-microvolt = <5000000>;
122*77f29293SSébastien Szymanski		regulator-max-microvolt = <5000000>;
123*77f29293SSébastien Szymanski		pinctrl-names = "default";
124*77f29293SSébastien Szymanski		pinctrl-0 = <&pinctrl_usbotg2_vbus>;
125*77f29293SSébastien Szymanski		gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
126*77f29293SSébastien Szymanski		enable-active-high;
127*77f29293SSébastien Szymanski	};
128*77f29293SSébastien Szymanski};
129*77f29293SSébastien Szymanski
130*77f29293SSébastien Szymanski&adc1 {
131*77f29293SSébastien Szymanski	vref-supply = <&reg_3v3>;
132*77f29293SSébastien Szymanski	status = "okay";
133*77f29293SSébastien Szymanski};
134*77f29293SSébastien Szymanski
135*77f29293SSébastien Szymanski&can1 {
136*77f29293SSébastien Szymanski	pinctrl-names = "default";
137*77f29293SSébastien Szymanski	pinctrl-0 = <&pinctrl_flexcan1>;
138*77f29293SSébastien Szymanski	xceiver-supply = <&reg_5v>;
139*77f29293SSébastien Szymanski	status = "okay";
140*77f29293SSébastien Szymanski};
141*77f29293SSébastien Szymanski
142*77f29293SSébastien Szymanski&can2 {
143*77f29293SSébastien Szymanski	pinctrl-names = "default";
144*77f29293SSébastien Szymanski	pinctrl-0 = <&pinctrl_flexcan2>;
145*77f29293SSébastien Szymanski	xceiver-supply = <&reg_5v>;
146*77f29293SSébastien Szymanski	status = "okay";
147*77f29293SSébastien Szymanski};
148*77f29293SSébastien Szymanski
149*77f29293SSébastien Szymanski&ecspi4 {
150*77f29293SSébastien Szymanski	pinctrl-names = "default";
151*77f29293SSébastien Szymanski	pinctrl-0 = <&pinctrl_ecspi4>;
152*77f29293SSébastien Szymanski	cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
153*77f29293SSébastien Szymanski	status = "okay";
154*77f29293SSébastien Szymanski
155*77f29293SSébastien Szymanski	spidev0: spi@0 {
156*77f29293SSébastien Szymanski		compatible = "spidev";
157*77f29293SSébastien Szymanski		reg = <0>;
158*77f29293SSébastien Szymanski		spi-max-frequency = <5000000>;
159*77f29293SSébastien Szymanski	};
160*77f29293SSébastien Szymanski
161*77f29293SSébastien Szymanski	spidev1: spi@1 {
162*77f29293SSébastien Szymanski		compatible = "spidev";
163*77f29293SSébastien Szymanski		reg = <1>;
164*77f29293SSébastien Szymanski		spi-max-frequency = <5000000>;
165*77f29293SSébastien Szymanski	};
166*77f29293SSébastien Szymanski};
167*77f29293SSébastien Szymanski
168*77f29293SSébastien Szymanski&i2c1 {
169*77f29293SSébastien Szymanski	pinctrl-names = "default";
170*77f29293SSébastien Szymanski	pinctrl-0 = <&pinctrl_i2c1>;
171*77f29293SSébastien Szymanski	clock_frequency = <400000>;
172*77f29293SSébastien Szymanski	status = "okay";
173*77f29293SSébastien Szymanski};
174*77f29293SSébastien Szymanski
175*77f29293SSébastien Szymanski&i2c2 {
176*77f29293SSébastien Szymanski	pinctrl-names = "default";
177*77f29293SSébastien Szymanski	pinctrl-0 = <&pinctrl_i2c2>;
178*77f29293SSébastien Szymanski	clock_frequency = <400000>;
179*77f29293SSébastien Szymanski	status = "okay";
180*77f29293SSébastien Szymanski};
181*77f29293SSébastien Szymanski
182*77f29293SSébastien Szymanski&lcdif {
183*77f29293SSébastien Szymanski	pinctrl-names = "default";
184*77f29293SSébastien Szymanski	pinctrl-0 = <&pinctrl_lcdif>;
185*77f29293SSébastien Szymanski	display = <&display0>;
186*77f29293SSébastien Szymanski	lcd-supply = <&reg_3v3>;
187*77f29293SSébastien Szymanski	status = "okay";
188*77f29293SSébastien Szymanski
189*77f29293SSébastien Szymanski	display0: display0 {
190*77f29293SSébastien Szymanski		bits-per-pixel = <32>;
191*77f29293SSébastien Szymanski		bus-width = <18>;
192*77f29293SSébastien Szymanski
193*77f29293SSébastien Szymanski		display-timings {
194*77f29293SSébastien Szymanski			timing0: timing0 {
195*77f29293SSébastien Szymanski				clock-frequency = <33000033>;
196*77f29293SSébastien Szymanski				hactive = <800>;
197*77f29293SSébastien Szymanski				vactive = <480>;
198*77f29293SSébastien Szymanski				hback-porch = <96>;
199*77f29293SSébastien Szymanski				hfront-porch = <96>;
200*77f29293SSébastien Szymanski				vback-porch = <20>;
201*77f29293SSébastien Szymanski				vfront-porch = <21>;
202*77f29293SSébastien Szymanski				hsync-len = <64>;
203*77f29293SSébastien Szymanski				vsync-len = <4>;
204*77f29293SSébastien Szymanski				de-active = <1>;
205*77f29293SSébastien Szymanski				pixelclk-active = <0>;
206*77f29293SSébastien Szymanski			};
207*77f29293SSébastien Szymanski		};
208*77f29293SSébastien Szymanski	};
209*77f29293SSébastien Szymanski};
210*77f29293SSébastien Szymanski
211*77f29293SSébastien Szymanski&pwm3 {
212*77f29293SSébastien Szymanski	pinctrl-names = "default";
213*77f29293SSébastien Szymanski	pinctrl-0 = <&pinctrl_pwm3>;
214*77f29293SSébastien Szymanski	status = "okay";
215*77f29293SSébastien Szymanski};
216*77f29293SSébastien Szymanski
217*77f29293SSébastien Szymanski&snvs_pwrkey {
218*77f29293SSébastien Szymanski	status = "disabled";
219*77f29293SSébastien Szymanski};
220*77f29293SSébastien Szymanski
221*77f29293SSébastien Szymanski&tsc {
222*77f29293SSébastien Szymanski	pinctrl-names = "default";
223*77f29293SSébastien Szymanski	pinctrl-0 = <&pinctrl_tsc>;
224*77f29293SSébastien Szymanski	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
225*77f29293SSébastien Szymanski	measure-delay-time = <0xffff>;
226*77f29293SSébastien Szymanski	pre-charge-time = <0xffff>;
227*77f29293SSébastien Szymanski	status = "okay";
228*77f29293SSébastien Szymanski};
229*77f29293SSébastien Szymanski
230*77f29293SSébastien Szymanski&uart1 {
231*77f29293SSébastien Szymanski	pinctrl-names = "default";
232*77f29293SSébastien Szymanski	pinctrl-0 = <&pinctrl_uart1>;
233*77f29293SSébastien Szymanski	status = "okay";
234*77f29293SSébastien Szymanski};
235*77f29293SSébastien Szymanski
236*77f29293SSébastien Szymanski&uart2 {
237*77f29293SSébastien Szymanski	pinctrl-names = "default";
238*77f29293SSébastien Szymanski	pinctrl-0 = <&pinctrl_uart2>;
239*77f29293SSébastien Szymanski	status = "okay";
240*77f29293SSébastien Szymanski};
241*77f29293SSébastien Szymanski
242*77f29293SSébastien Szymanski&usbotg1 {
243*77f29293SSébastien Szymanski	pinctrl-names = "default";
244*77f29293SSébastien Szymanski	pinctrl-0 = <&pinctrl_usbotg1_id>;
245*77f29293SSébastien Szymanski	vbus-supply = <&reg_usbotg1_vbus>;
246*77f29293SSébastien Szymanski	dr_mode = "otg";
247*77f29293SSébastien Szymanski	disable-over-current;
248*77f29293SSébastien Szymanski	status = "okay";
249*77f29293SSébastien Szymanski};
250*77f29293SSébastien Szymanski
251*77f29293SSébastien Szymanski&usbotg2 {
252*77f29293SSébastien Szymanski	vbus-supply = <&reg_usbotg2_vbus>;
253*77f29293SSébastien Szymanski	dr_mode = "host";
254*77f29293SSébastien Szymanski	disable-over-current;
255*77f29293SSébastien Szymanski	status = "okay";
256*77f29293SSébastien Szymanski};
257*77f29293SSébastien Szymanski
258*77f29293SSébastien Szymanski&iomuxc {
259*77f29293SSébastien Szymanski	pinctrl-names = "default";
260*77f29293SSébastien Szymanski	pinctrl-0 = <&pinctrl_gpios>;
261*77f29293SSébastien Szymanski
262*77f29293SSébastien Szymanski	pinctrl_ecspi4: ecspi4grp {
263*77f29293SSébastien Szymanski		fsl,pins = <
264*77f29293SSébastien Szymanski			MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK	0x1b0b0
265*77f29293SSébastien Szymanski			MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI	0x1b0b0
266*77f29293SSébastien Szymanski			MX6UL_PAD_NAND_DATA06__ECSPI4_MISO	0x1b0b0
267*77f29293SSébastien Szymanski			MX6UL_PAD_NAND_DATA01__GPIO4_IO03	0x1b0b0
268*77f29293SSébastien Szymanski			MX6UL_PAD_NAND_DATA07__GPIO4_IO09	0x1b0b0
269*77f29293SSébastien Szymanski		>;
270*77f29293SSébastien Szymanski	};
271*77f29293SSébastien Szymanski
272*77f29293SSébastien Szymanski	pinctrl_flexcan1: flexcan1grp {
273*77f29293SSébastien Szymanski		fsl,pins = <
274*77f29293SSébastien Szymanski			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x0b0b0
275*77f29293SSébastien Szymanski			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x0b0b0
276*77f29293SSébastien Szymanski		>;
277*77f29293SSébastien Szymanski	};
278*77f29293SSébastien Szymanski
279*77f29293SSébastien Szymanski	pinctrl_flexcan2: flexcan2grp {
280*77f29293SSébastien Szymanski		fsl,pins = <
281*77f29293SSébastien Szymanski			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x0b0b0
282*77f29293SSébastien Szymanski			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x0b0b0
283*77f29293SSébastien Szymanski		>;
284*77f29293SSébastien Szymanski	};
285*77f29293SSébastien Szymanski
286*77f29293SSébastien Szymanski	pinctrl_gpios: gpiosgrp {
287*77f29293SSébastien Szymanski		fsl,pins = <
288*77f29293SSébastien Szymanski			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09	0x0b0b0
289*77f29293SSébastien Szymanski			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x0b0b0
290*77f29293SSébastien Szymanski			MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x0b0b0
291*77f29293SSébastien Szymanski			MX6UL_PAD_NAND_RE_B__GPIO4_IO00		0x0b0b0
292*77f29293SSébastien Szymanski			MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0x0b0b0
293*77f29293SSébastien Szymanski			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x0b0b0
294*77f29293SSébastien Szymanski			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x0b0b0
295*77f29293SSébastien Szymanski			MX6UL_PAD_NAND_WE_B__GPIO4_IO01		0x0b0b0
296*77f29293SSébastien Szymanski			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x0b0b0
297*77f29293SSébastien Szymanski			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x0b0b0
298*77f29293SSébastien Szymanski			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x0b0b0
299*77f29293SSébastien Szymanski			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x0b0b0
300*77f29293SSébastien Szymanski			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x0b0b0
301*77f29293SSébastien Szymanski			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x0b0b0
302*77f29293SSébastien Szymanski			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x0b0b0
303*77f29293SSébastien Szymanski			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x0b0b0
304*77f29293SSébastien Szymanski		>;
305*77f29293SSébastien Szymanski	};
306*77f29293SSébastien Szymanski
307*77f29293SSébastien Szymanski	pinctrl_gpio_keys: gpiokeysgrp {
308*77f29293SSébastien Szymanski		fsl,pins = <
309*77f29293SSébastien Szymanski			MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11	0x0b0b0
310*77f29293SSébastien Szymanski		>;
311*77f29293SSébastien Szymanski	};
312*77f29293SSébastien Szymanski
313*77f29293SSébastien Szymanski	pinctrl_i2c1: i2c1grp {
314*77f29293SSébastien Szymanski		fsl,pins = <
315*77f29293SSébastien Szymanski			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA	0x4001b8b0
316*77f29293SSébastien Szymanski			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL	0x4001b8b0
317*77f29293SSébastien Szymanski		>;
318*77f29293SSébastien Szymanski	};
319*77f29293SSébastien Szymanski
320*77f29293SSébastien Szymanski	pinctrl_i2c2: i2c2grp {
321*77f29293SSébastien Szymanski		fsl,pins = <
322*77f29293SSébastien Szymanski			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001b8b0
323*77f29293SSébastien Szymanski			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001b8b0
324*77f29293SSébastien Szymanski		>;
325*77f29293SSébastien Szymanski	};
326*77f29293SSébastien Szymanski
327*77f29293SSébastien Szymanski	pinctrl_lcdif: lcdifgrp {
328*77f29293SSébastien Szymanski		fsl,pins = <
329*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x100b1
330*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x100b1
331*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x100b1
332*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x100b1
333*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x100b1
334*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x100b1
335*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x100b1
336*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x100b1
337*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x100b1
338*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x100b1
339*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x100b1
340*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x100b1
341*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x100b1
342*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x100b1
343*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x100b1
344*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x100b1
345*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x100b1
346*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x100b1
347*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x100b1
348*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x100b1
349*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x100b1
350*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x100b1
351*77f29293SSébastien Szymanski		>;
352*77f29293SSébastien Szymanski	};
353*77f29293SSébastien Szymanski
354*77f29293SSébastien Szymanski	pinctrl_led: ledgrp {
355*77f29293SSébastien Szymanski		fsl,pins = <
356*77f29293SSébastien Szymanski			MX6UL_PAD_LCD_RESET__GPIO3_IO04		0x0b0b0
357*77f29293SSébastien Szymanski		>;
358*77f29293SSébastien Szymanski	};
359*77f29293SSébastien Szymanski
360*77f29293SSébastien Szymanski	pinctrl_pwm3: pwm3grp {
361*77f29293SSébastien Szymanski		fsl,pins = <
362*77f29293SSébastien Szymanski			MX6UL_PAD_NAND_ALE__PWM3_OUT		0x1b0b0
363*77f29293SSébastien Szymanski		>;
364*77f29293SSébastien Szymanski	};
365*77f29293SSébastien Szymanski
366*77f29293SSébastien Szymanski	pinctrl_tsc: tscgrp {
367*77f29293SSébastien Szymanski		fsl,pins = <
368*77f29293SSébastien Szymanski			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01       0xb0
369*77f29293SSébastien Szymanski			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02       0xb0
370*77f29293SSébastien Szymanski			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03       0xb0
371*77f29293SSébastien Szymanski			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04       0xb0
372*77f29293SSébastien Szymanski		>;
373*77f29293SSébastien Szymanski	};
374*77f29293SSébastien Szymanski
375*77f29293SSébastien Szymanski	pinctrl_uart1: uart1grp {
376*77f29293SSébastien Szymanski		fsl,pins = <
377*77f29293SSébastien Szymanski			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
378*77f29293SSébastien Szymanski			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
379*77f29293SSébastien Szymanski		>;
380*77f29293SSébastien Szymanski	};
381*77f29293SSébastien Szymanski
382*77f29293SSébastien Szymanski	pinctrl_uart2: uart2grp {
383*77f29293SSébastien Szymanski		fsl,pins = <
384*77f29293SSébastien Szymanski			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
385*77f29293SSébastien Szymanski			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
386*77f29293SSébastien Szymanski		>;
387*77f29293SSébastien Szymanski	};
388*77f29293SSébastien Szymanski
389*77f29293SSébastien Szymanski	pinctrl_usbotg1_id: usbotg1idgrp {
390*77f29293SSébastien Szymanski		fsl,pins = <
391*77f29293SSébastien Szymanski			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x1b0b0
392*77f29293SSébastien Szymanski		>;
393*77f29293SSébastien Szymanski	};
394*77f29293SSébastien Szymanski
395*77f29293SSébastien Szymanski	pinctrl_usbotg1_vbus: usbotg1vbusgrp {
396*77f29293SSébastien Szymanski		fsl,pins = <
397*77f29293SSébastien Szymanski			MX6UL_PAD_GPIO1_IO05__GPIO1_IO05	0x1b0b0
398*77f29293SSébastien Szymanski		>;
399*77f29293SSébastien Szymanski	};
400*77f29293SSébastien Szymanski
401*77f29293SSébastien Szymanski	pinctrl_usbotg2_vbus: usbotg2vbusgrp {
402*77f29293SSébastien Szymanski		fsl,pins = <
403*77f29293SSébastien Szymanski			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x1b0b0
404*77f29293SSébastien Szymanski		>;
405*77f29293SSébastien Szymanski	};
406*77f29293SSébastien Szymanski
407*77f29293SSébastien Szymanski	pinctrl_w1: w1grp {
408*77f29293SSébastien Szymanski		fsl,pins = <
409*77f29293SSébastien Szymanski			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x0b0b0
410*77f29293SSébastien Szymanski		>;
411*77f29293SSébastien Szymanski	};
412*77f29293SSébastien Szymanski};
413