xref: /openbmc/u-boot/arch/arm/dts/imx6ul-isiot.dtsi (revision 77f29293)
1/*
2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This file is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License
12 *     version 2 as published by the Free Software Foundation.
13 *
14 *     This file is distributed in the hope that it will be useful
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44
45#include <dt-bindings/gpio/gpio.h>
46#include <dt-bindings/input/input.h>
47#include "imx6ul.dtsi"
48
49/ {
50	memory {
51		reg = <0x80000000 0x20000000>;
52	};
53
54	chosen {
55		stdout-path = &uart1;
56	};
57};
58
59&fec1 {
60	pinctrl-names = "default";
61	pinctrl-0 = <&pinctrl_enet1>;
62	phy-mode = "rmii";
63	status = "okay";
64};
65
66&i2c1 {
67	clock-frequency = <100000>;
68	pinctrl-names = "default";
69	pinctrl-0 = <&pinctrl_i2c1>;
70	status = "okay";
71};
72
73&i2c2 {
74	clock_frequency = <100000>;
75	pinctrl-names = "default";
76	pinctrl-0 = <&pinctrl_i2c2>;
77	status = "okay";
78};
79
80&uart1 {
81	pinctrl-names = "default";
82	pinctrl-0 = <&pinctrl_uart1>;
83	status = "okay";
84};
85
86&usdhc1 {
87	pinctrl-names = "default";
88	pinctrl-0 = <&pinctrl_usdhc1>;
89	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
90	bus-width = <4>;
91	no-1-8-v;
92	status = "okay";
93};
94
95&iomuxc {
96	pinctrl_enet1: enet1grp {
97		fsl,pins = <
98			MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO    0x1b0b0
99			MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC     0x1b0b0
100			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
101			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
102			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
103			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
104			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
105			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
106			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
107			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10       0x1b0b0
108		>;
109	};
110
111	pinctrl_i2c1: i2c1grp {
112		fsl,pins = <
113			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
114			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
115		>;
116	};
117
118	pinctrl_i2c2: i2c2grp {
119			fsl,pins = <
120			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
121			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
122		>;
123	};
124
125	pinctrl_uart1: uart1grp {
126		fsl,pins = <
127			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
128			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
129		>;
130	};
131
132	pinctrl_usdhc1: usdhc1grp {
133		fsl,pins = <
134			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
135			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
136			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
137			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
138			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
139			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
140		>;
141	};
142};
143