xref: /openbmc/u-boot/arch/arm/dts/imx6ul-isiot.dtsi (revision 3eceff64)

/*
 * Copyright (C) 2016 Amarula Solutions B.V.
 * Copyright (C) 2016 Engicam S.r.l.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	memory {
		reg = <0x80000000 0x20000000>;
	};

	chosen {
		stdout-path = &uart1;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock_frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	no-1-8-v;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
	bus-width = <8>;
	no-1-8-v;
	status = "disabled";
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO    0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC     0x1b0b0
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10       0x1b0b0
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
		>;
	};

	pinctrl_i2c2: i2c2grp {
			fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		u-boot,dm-spl;
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
		>;
	};
};