1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
5 */
6
7/dts-v1/;
8
9#include "imx6ul.dtsi"
10
11/ {
12	model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
13	compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
14
15	aliases {
16		spi5 = &soft_spi;
17	};
18
19	chosen {
20		stdout-path = &uart1;
21	};
22
23	memory {
24		reg = <0x80000000 0x20000000>;
25	};
26
27	regulators {
28		compatible = "simple-bus";
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		reg_sd1_vmmc: regulator@1 {
33			compatible = "regulator-fixed";
34			regulator-name = "VSD_3V3";
35			regulator-min-microvolt = <3300000>;
36			regulator-max-microvolt = <3300000>;
37			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
38			off-on-delay = <20000>;
39			enable-active-high;
40		};
41
42		reg_can_3v3: regulator@0 {
43			compatible = "regulator-fixed";
44			reg = <0>;
45			regulator-name = "can-3v3";
46			regulator-min-microvolt = <3300000>;
47			regulator-max-microvolt = <3300000>;
48			gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
49		};
50
51		reg_gpio_dvfs: regulator-gpio {
52			compatible = "regulator-gpio";
53			pinctrl-names = "default";
54			pinctrl-0 = <&pinctrl_dvfs>;
55			regulator-min-microvolt = <1300000>;
56			regulator-max-microvolt = <1400000>;
57			regulator-name = "gpio_dvfs";
58			regulator-type = "voltage";
59			gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
60			states = <1300000 0x1 1400000 0x0>;
61		};
62	};
63
64	soft_spi: soft-spi {
65		compatible = "spi-gpio";
66		pinctrl-names = "default";
67		pinctrl-0 = <&pinctrl_spi4>;
68		pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
69		status = "okay";
70		gpio-sck = <&gpio5 11 0>;
71		gpio-mosi = <&gpio5 10 0>;
72		cs-gpios = <&gpio5 7 0>;
73		num-chipselects = <1>;
74		#address-cells = <1>;
75		#size-cells = <0>;
76
77		gpio_spi: gpio_spi@0 {
78			compatible = "fairchild,74hc595";
79			gpio-controller;
80			#gpio-cells = <2>;
81			reg = <0>;
82			registers-number = <1>;
83			registers-default = /bits/ 8 <0x57>;
84			spi-max-frequency = <100000>;
85		};
86	};
87};
88
89&fec1 {
90	pinctrl-names = "default";
91	pinctrl-0 = <&pinctrl_enet1>;
92	phy-mode = "rmii";
93	phy-handle = <&ethphy0>;
94	status = "okay";
95};
96
97&fec2 {
98	pinctrl-names = "default";
99	pinctrl-0 = <&pinctrl_enet2>;
100	phy-mode = "rmii";
101	phy-handle = <&ethphy1>;
102	status = "okay";
103
104	mdio {
105		#address-cells = <1>;
106		#size-cells = <0>;
107
108		ethphy0: ethernet-phy@2 {
109			compatible = "ethernet-phy-ieee802.3-c22";
110			reg = <2>;
111		};
112
113		ethphy1: ethernet-phy@1 {
114			compatible = "ethernet-phy-ieee802.3-c22";
115			reg = <1>;
116		};
117	};
118};
119
120&i2c1 {
121	clock-frequency = <100000>;
122	pinctrl-names = "default", "gpio";
123	pinctrl-0 = <&pinctrl_i2c1>;
124	pinctrl-1 = <&pinctrl_i2c1_gpio>;
125	scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
126	sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
127	status = "okay";
128
129	mag3110@0e {
130		compatible = "fsl,mag3110";
131		reg = <0x0e>;
132		position = <2>;
133	};
134
135	fxls8471@1e {
136		compatible = "fsl,fxls8471";
137		reg = <0x1e>;
138		position = <0>;
139		interrupt-parent = <&gpio5>;
140		interrupts = <0 8>;
141	};
142};
143
144&i2c2 {
145	clock_frequency = <100000>;
146	pinctrl-names = "default", "gpio";
147	pinctrl-0 = <&pinctrl_i2c2>;
148	pinctrl-1 = <&pinctrl_i2c2_gpio>;
149	scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
150	sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
151	status = "okay";
152};
153
154&iomuxc {
155	pinctrl-names = "default";
156	pinctrl-0 = <&pinctrl_hog_1>;
157	imx6ul-evk {
158		pinctrl_hog_1: hoggrp-1 {
159			fsl,pins = <
160				MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059 /* SD1 CD */
161				MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059 /* SD1 VSELECT */
162				MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
163				MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x80000000
164			>;
165		};
166
167		pinctrl_dvfs: dvfsgrp {
168			fsl,pins = <
169				MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x79
170			>;
171		};
172
173		pinctrl_enet1: enet1grp {
174			fsl,pins = <
175				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
176				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
177				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
178				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
179				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
180				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
181				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
182				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
183			>;
184		};
185
186		pinctrl_enet2: enet2grp {
187			fsl,pins = <
188				MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
189				MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
190				MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
191				MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
192				MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
193				MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
194				MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
195				MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
196				MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
197				MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
198			>;
199		};
200
201		pinctrl_i2c1: i2c1grp {
202			fsl,pins = <
203				MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
204				MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
205			>;
206		};
207
208		pinctrl_i2c1_gpio: i2c1grp_gpio {
209			fsl,pins = <
210				MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
211				MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
212			>;
213		};
214
215		pinctrl_i2c2: i2c2grp {
216			fsl,pins = <
217				MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
218				MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
219			>;
220		};
221
222		pinctrl_i2c2_gpio: i2c2grp_gpio {
223			fsl,pins = <
224				MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
225				MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
226			>;
227		};
228
229		pinctrl_qspi: qspigrp {
230			fsl,pins = <
231				MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
232				MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
233				MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
234				MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
235				MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
236				MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
237			>;
238		};
239
240		pinctrl_spi4: spi4grp {
241			fsl,pins = <
242				MX6UL_PAD_BOOT_MODE0__GPIO5_IO10	0x70a1
243				MX6UL_PAD_BOOT_MODE1__GPIO5_IO11	0x70a1
244				MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x70a1
245				MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x80000000
246			>;
247		};
248
249		pinctrl_uart1: uart1grp {
250			fsl,pins = <
251				MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
252				MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
253			>;
254		};
255
256		pinctrl_usb_otg1_id: usbotg1idgrp {
257			fsl,pins = <
258				MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
259			>;
260		};
261
262		pinctrl_usdhc1: usdhc1grp {
263			fsl,pins = <
264				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
265				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10071
266				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
267				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
268				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
269				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
270			>;
271		};
272
273		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
274			fsl,pins = <
275				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
276				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
277				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
278				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
279				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
280				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
281			>;
282		};
283
284		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
285			fsl,pins = <
286				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
287				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
288				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
289				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
290				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
291				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
292			>;
293		};
294
295		pinctrl_usdhc2: usdhc2grp {
296			fsl,pins = <
297				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
298				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
299				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
300				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
301				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
302				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
303			>;
304		};
305
306		pinctrl_usdhc2_8bit: usdhc2grp_8bit {
307			fsl,pins = <
308				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
309				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
310				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
311				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
312				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
313				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
314				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
315				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
316				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
317				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
318			>;
319		};
320
321		pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
322			fsl,pins = <
323				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
324				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
325				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
326				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
327				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
328				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
329				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
330				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
331				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
332				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
333			>;
334		};
335
336		pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
337			fsl,pins = <
338				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
339				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
340				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
341				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
342				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
343				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
344				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
345				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
346				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
347				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
348			>;
349		};
350		pinctrl_wdog: wdoggrp {
351			fsl,pins = <
352				MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
353			>;
354		};
355	};
356};
357
358&qspi {
359	pinctrl-names = "default";
360	pinctrl-0 = <&pinctrl_qspi>;
361	status = "okay";
362	ddrsmp=<0>;
363
364	flash0: n25q256a@0 {
365		#address-cells = <1>;
366		#size-cells = <1>;
367		compatible = "micron,n25q256a";
368		spi-max-frequency = <29000000>;
369		spi-nor,ddr-quad-read-dummy = <6>;
370		reg = <0>;
371	};
372};
373
374&uart1 {
375	pinctrl-names = "default";
376	pinctrl-0 = <&pinctrl_uart1>;
377	status = "okay";
378};
379
380&usbotg1 {
381	pinctrl-names = "default";
382	pinctrl-0 = <&pinctrl_usb_otg1_id>;
383	dr_mode = "otg";
384	srp-disable;
385	hnp-disable;
386	adp-disable;
387	status = "okay";
388};
389
390&usbotg2 {
391	dr_mode = "host";
392	disable-over-current;
393	status = "okay";
394};
395
396&usbphy1 {
397	tx-d-cal = <0x5>;
398};
399
400&usbphy2 {
401	tx-d-cal = <0x5>;
402};
403
404&usdhc1 {
405	pinctrl-names = "default", "state_100mhz", "state_200mhz";
406	pinctrl-0 = <&pinctrl_usdhc1>;
407	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
408	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
409	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
410	keep-power-in-suspend;
411	wakeup-source;
412	vmmc-supply = <&reg_sd1_vmmc>;
413	status = "okay";
414};
415
416&usdhc2 {
417	pinctrl-names = "default";
418	pinctrl-0 = <&pinctrl_usdhc2>;
419	non-removable;
420	status = "okay";
421};
422
423&wdog1 {
424	pinctrl-names = "default";
425	pinctrl-0 = <&pinctrl_wdog>;
426	fsl,ext-reset-output;
427};
428