1/* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#include <dt-bindings/clock/imx6sx-clock.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include "imx6sx-pinfunc.h" 14#include "skeleton.dtsi" 15 16/ { 17 aliases { 18 can0 = &flexcan1; 19 can1 = &flexcan2; 20 ethernet0 = &fec1; 21 ethernet1 = &fec2; 22 gpio0 = &gpio1; 23 gpio1 = &gpio2; 24 gpio2 = &gpio3; 25 gpio3 = &gpio4; 26 gpio4 = &gpio5; 27 gpio5 = &gpio6; 28 gpio6 = &gpio7; 29 i2c0 = &i2c1; 30 i2c1 = &i2c2; 31 i2c2 = &i2c3; 32 i2c3 = &i2c4; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 mmc2 = &usdhc3; 36 mmc3 = &usdhc4; 37 serial0 = &uart1; 38 serial1 = &uart2; 39 serial2 = &uart3; 40 serial3 = &uart4; 41 serial4 = &uart5; 42 serial5 = &uart6; 43 spi0 = &qspi1; 44 spi1 = &qspi2; 45 spi2 = &ecspi1; 46 spi3 = &ecspi2; 47 spi4 = &ecspi3; 48 spi5 = &ecspi4; 49 spi6 = &ecspi5; 50 usbphy0 = &usbphy1; 51 usbphy1 = &usbphy2; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a9"; 60 device_type = "cpu"; 61 reg = <0>; 62 next-level-cache = <&L2>; 63 operating-points = < 64 /* kHz uV */ 65 996000 1250000 66 792000 1175000 67 396000 1075000 68 198000 975000 69 >; 70 fsl,soc-operating-points = < 71 /* ARM kHz SOC uV */ 72 996000 1175000 73 792000 1175000 74 396000 1175000 75 198000 1175000 76 >; 77 clock-latency = <61036>; /* two CLK32 periods */ 78 clocks = <&clks IMX6SX_CLK_ARM>, 79 <&clks IMX6SX_CLK_PLL2_PFD2>, 80 <&clks IMX6SX_CLK_STEP>, 81 <&clks IMX6SX_CLK_PLL1_SW>, 82 <&clks IMX6SX_CLK_PLL1_SYS>; 83 clock-names = "arm", "pll2_pfd2_396m", "step", 84 "pll1_sw", "pll1_sys"; 85 arm-supply = <®_arm>; 86 soc-supply = <®_soc>; 87 }; 88 }; 89 90 intc: interrupt-controller@00a01000 { 91 compatible = "arm,cortex-a9-gic"; 92 #interrupt-cells = <3>; 93 interrupt-controller; 94 reg = <0x00a01000 0x1000>, 95 <0x00a00100 0x100>; 96 interrupt-parent = <&intc>; 97 }; 98 99 clocks { 100 #address-cells = <1>; 101 #size-cells = <0>; 102 103 ckil: clock@0 { 104 compatible = "fixed-clock"; 105 reg = <0>; 106 #clock-cells = <0>; 107 clock-frequency = <32768>; 108 clock-output-names = "ckil"; 109 }; 110 111 osc: clock@1 { 112 compatible = "fixed-clock"; 113 reg = <1>; 114 #clock-cells = <0>; 115 clock-frequency = <24000000>; 116 clock-output-names = "osc"; 117 }; 118 119 ipp_di0: clock@2 { 120 compatible = "fixed-clock"; 121 reg = <2>; 122 #clock-cells = <0>; 123 clock-frequency = <0>; 124 clock-output-names = "ipp_di0"; 125 }; 126 127 ipp_di1: clock@3 { 128 compatible = "fixed-clock"; 129 reg = <3>; 130 #clock-cells = <0>; 131 clock-frequency = <0>; 132 clock-output-names = "ipp_di1"; 133 }; 134 }; 135 136 soc { 137 #address-cells = <1>; 138 #size-cells = <1>; 139 compatible = "simple-bus"; 140 interrupt-parent = <&gpc>; 141 ranges; 142 143 pmu { 144 compatible = "arm,cortex-a9-pmu"; 145 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 146 }; 147 148 ocram: sram@00900000 { 149 compatible = "mmio-sram"; 150 reg = <0x00900000 0x20000>; 151 clocks = <&clks IMX6SX_CLK_OCRAM>; 152 }; 153 154 L2: l2-cache@00a02000 { 155 compatible = "arm,pl310-cache"; 156 reg = <0x00a02000 0x1000>; 157 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 158 cache-unified; 159 cache-level = <2>; 160 arm,tag-latency = <4 2 3>; 161 arm,data-latency = <4 2 3>; 162 }; 163 164 gpu: gpu@01800000 { 165 compatible = "vivante,gc"; 166 reg = <0x01800000 0x4000>; 167 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 168 clocks = <&clks IMX6SX_CLK_GPU>, 169 <&clks IMX6SX_CLK_GPU>, 170 <&clks IMX6SX_CLK_GPU>; 171 clock-names = "bus", "core", "shader"; 172 }; 173 174 dma_apbh: dma-apbh@01804000 { 175 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; 176 reg = <0x01804000 0x2000>; 177 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 181 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 182 #dma-cells = <1>; 183 dma-channels = <4>; 184 clocks = <&clks IMX6SX_CLK_APBH_DMA>; 185 }; 186 187 gpmi: gpmi-nand@01806000{ 188 compatible = "fsl,imx6sx-gpmi-nand"; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 reg = <0x01806000 0x2000>, <0x01808000 0x4000>; 192 reg-names = "gpmi-nand", "bch"; 193 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-names = "bch"; 195 clocks = <&clks IMX6SX_CLK_GPMI_IO>, 196 <&clks IMX6SX_CLK_GPMI_APB>, 197 <&clks IMX6SX_CLK_GPMI_BCH>, 198 <&clks IMX6SX_CLK_GPMI_BCH_APB>, 199 <&clks IMX6SX_CLK_PER1_BCH>; 200 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 201 "gpmi_bch_apb", "per1_bch"; 202 dmas = <&dma_apbh 0>; 203 dma-names = "rx-tx"; 204 status = "disabled"; 205 }; 206 207 aips1: aips-bus@02000000 { 208 compatible = "fsl,aips-bus", "simple-bus"; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 reg = <0x02000000 0x100000>; 212 ranges; 213 214 spba-bus@02000000 { 215 compatible = "fsl,spba-bus", "simple-bus"; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 reg = <0x02000000 0x40000>; 219 ranges; 220 221 spdif: spdif@02004000 { 222 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; 223 reg = <0x02004000 0x4000>; 224 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 225 dmas = <&sdma 14 18 0>, 226 <&sdma 15 18 0>; 227 dma-names = "rx", "tx"; 228 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, 229 <&clks IMX6SX_CLK_OSC>, 230 <&clks IMX6SX_CLK_SPDIF>, 231 <&clks 0>, <&clks 0>, <&clks 0>, 232 <&clks IMX6SX_CLK_IPG>, 233 <&clks 0>, <&clks 0>, 234 <&clks IMX6SX_CLK_SPBA>; 235 clock-names = "core", "rxtx0", 236 "rxtx1", "rxtx2", 237 "rxtx3", "rxtx4", 238 "rxtx5", "rxtx6", 239 "rxtx7", "spba"; 240 status = "disabled"; 241 }; 242 243 ecspi1: ecspi@02008000 { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 247 reg = <0x02008000 0x4000>; 248 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&clks IMX6SX_CLK_ECSPI1>, 250 <&clks IMX6SX_CLK_ECSPI1>; 251 clock-names = "ipg", "per"; 252 status = "disabled"; 253 }; 254 255 ecspi2: ecspi@0200c000 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 259 reg = <0x0200c000 0x4000>; 260 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&clks IMX6SX_CLK_ECSPI2>, 262 <&clks IMX6SX_CLK_ECSPI2>; 263 clock-names = "ipg", "per"; 264 status = "disabled"; 265 }; 266 267 ecspi3: ecspi@02010000 { 268 #address-cells = <1>; 269 #size-cells = <0>; 270 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 271 reg = <0x02010000 0x4000>; 272 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&clks IMX6SX_CLK_ECSPI3>, 274 <&clks IMX6SX_CLK_ECSPI3>; 275 clock-names = "ipg", "per"; 276 status = "disabled"; 277 }; 278 279 ecspi4: ecspi@02014000 { 280 #address-cells = <1>; 281 #size-cells = <0>; 282 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 283 reg = <0x02014000 0x4000>; 284 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&clks IMX6SX_CLK_ECSPI4>, 286 <&clks IMX6SX_CLK_ECSPI4>; 287 clock-names = "ipg", "per"; 288 status = "disabled"; 289 }; 290 291 uart1: serial@02020000 { 292 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; 293 reg = <0x02020000 0x4000>; 294 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&clks IMX6SX_CLK_UART_IPG>, 296 <&clks IMX6SX_CLK_UART_SERIAL>; 297 clock-names = "ipg", "per"; 298 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 299 dma-names = "rx", "tx"; 300 status = "disabled"; 301 }; 302 303 esai: esai@02024000 { 304 reg = <0x02024000 0x4000>; 305 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&clks IMX6SX_CLK_ESAI_IPG>, 307 <&clks IMX6SX_CLK_ESAI_MEM>, 308 <&clks IMX6SX_CLK_ESAI_EXTAL>, 309 <&clks IMX6SX_CLK_ESAI_IPG>, 310 <&clks IMX6SX_CLK_SPBA>; 311 clock-names = "core", "mem", "extal", 312 "fsys", "spba"; 313 status = "disabled"; 314 }; 315 316 ssi1: ssi@02028000 { 317 #sound-dai-cells = <0>; 318 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 319 reg = <0x02028000 0x4000>; 320 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&clks IMX6SX_CLK_SSI1_IPG>, 322 <&clks IMX6SX_CLK_SSI1>; 323 clock-names = "ipg", "baud"; 324 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; 325 dma-names = "rx", "tx"; 326 fsl,fifo-depth = <15>; 327 status = "disabled"; 328 }; 329 330 ssi2: ssi@0202c000 { 331 #sound-dai-cells = <0>; 332 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 333 reg = <0x0202c000 0x4000>; 334 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&clks IMX6SX_CLK_SSI2_IPG>, 336 <&clks IMX6SX_CLK_SSI2>; 337 clock-names = "ipg", "baud"; 338 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; 339 dma-names = "rx", "tx"; 340 fsl,fifo-depth = <15>; 341 status = "disabled"; 342 }; 343 344 ssi3: ssi@02030000 { 345 #sound-dai-cells = <0>; 346 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 347 reg = <0x02030000 0x4000>; 348 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&clks IMX6SX_CLK_SSI3_IPG>, 350 <&clks IMX6SX_CLK_SSI3>; 351 clock-names = "ipg", "baud"; 352 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; 353 dma-names = "rx", "tx"; 354 fsl,fifo-depth = <15>; 355 status = "disabled"; 356 }; 357 358 asrc: asrc@02034000 { 359 reg = <0x02034000 0x4000>; 360 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&clks IMX6SX_CLK_ASRC_MEM>, 362 <&clks IMX6SX_CLK_ASRC_IPG>, 363 <&clks IMX6SX_CLK_SPDIF>, 364 <&clks IMX6SX_CLK_SPBA>; 365 clock-names = "mem", "ipg", "asrck", "spba"; 366 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, 367 <&sdma 19 20 1>, <&sdma 20 20 1>, 368 <&sdma 21 20 1>, <&sdma 22 20 1>; 369 dma-names = "rxa", "rxb", "rxc", 370 "txa", "txb", "txc"; 371 status = "okay"; 372 }; 373 }; 374 375 pwm1: pwm@02080000 { 376 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 377 reg = <0x02080000 0x4000>; 378 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&clks IMX6SX_CLK_PWM1>, 380 <&clks IMX6SX_CLK_PWM1>; 381 clock-names = "ipg", "per"; 382 #pwm-cells = <2>; 383 }; 384 385 pwm2: pwm@02084000 { 386 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 387 reg = <0x02084000 0x4000>; 388 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clks IMX6SX_CLK_PWM2>, 390 <&clks IMX6SX_CLK_PWM2>; 391 clock-names = "ipg", "per"; 392 #pwm-cells = <2>; 393 }; 394 395 pwm3: pwm@02088000 { 396 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 397 reg = <0x02088000 0x4000>; 398 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&clks IMX6SX_CLK_PWM3>, 400 <&clks IMX6SX_CLK_PWM3>; 401 clock-names = "ipg", "per"; 402 #pwm-cells = <2>; 403 }; 404 405 pwm4: pwm@0208c000 { 406 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 407 reg = <0x0208c000 0x4000>; 408 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&clks IMX6SX_CLK_PWM4>, 410 <&clks IMX6SX_CLK_PWM4>; 411 clock-names = "ipg", "per"; 412 #pwm-cells = <2>; 413 }; 414 415 flexcan1: can@02090000 { 416 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 417 reg = <0x02090000 0x4000>; 418 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&clks IMX6SX_CLK_CAN1_IPG>, 420 <&clks IMX6SX_CLK_CAN1_SERIAL>; 421 clock-names = "ipg", "per"; 422 status = "disabled"; 423 }; 424 425 flexcan2: can@02094000 { 426 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 427 reg = <0x02094000 0x4000>; 428 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&clks IMX6SX_CLK_CAN2_IPG>, 430 <&clks IMX6SX_CLK_CAN2_SERIAL>; 431 clock-names = "ipg", "per"; 432 status = "disabled"; 433 }; 434 435 gpt: gpt@02098000 { 436 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt"; 437 reg = <0x02098000 0x4000>; 438 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&clks IMX6SX_CLK_GPT_BUS>, 440 <&clks IMX6SX_CLK_GPT_3M>; 441 clock-names = "ipg", "per"; 442 }; 443 444 gpio1: gpio@0209c000 { 445 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 446 reg = <0x0209c000 0x4000>; 447 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 449 gpio-controller; 450 #gpio-cells = <2>; 451 interrupt-controller; 452 #interrupt-cells = <2>; 453 gpio-ranges = <&iomuxc 0 5 26>; 454 }; 455 456 gpio2: gpio@020a0000 { 457 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 458 reg = <0x020a0000 0x4000>; 459 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 461 gpio-controller; 462 #gpio-cells = <2>; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 gpio-ranges = <&iomuxc 0 31 20>; 466 }; 467 468 gpio3: gpio@020a4000 { 469 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 470 reg = <0x020a4000 0x4000>; 471 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 473 gpio-controller; 474 #gpio-cells = <2>; 475 interrupt-controller; 476 #interrupt-cells = <2>; 477 gpio-ranges = <&iomuxc 0 51 29>; 478 }; 479 480 gpio4: gpio@020a8000 { 481 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 482 reg = <0x020a8000 0x4000>; 483 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 485 gpio-controller; 486 #gpio-cells = <2>; 487 interrupt-controller; 488 #interrupt-cells = <2>; 489 gpio-ranges = <&iomuxc 0 80 32>; 490 }; 491 492 gpio5: gpio@020ac000 { 493 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 494 reg = <0x020ac000 0x4000>; 495 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 497 gpio-controller; 498 #gpio-cells = <2>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 gpio-ranges = <&iomuxc 0 112 24>; 502 }; 503 504 gpio6: gpio@020b0000 { 505 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 506 reg = <0x020b0000 0x4000>; 507 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 509 gpio-controller; 510 #gpio-cells = <2>; 511 interrupt-controller; 512 #interrupt-cells = <2>; 513 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; 514 }; 515 516 gpio7: gpio@020b4000 { 517 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 518 reg = <0x020b4000 0x4000>; 519 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 521 gpio-controller; 522 #gpio-cells = <2>; 523 interrupt-controller; 524 #interrupt-cells = <2>; 525 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; 526 }; 527 528 kpp: kpp@020b8000 { 529 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; 530 reg = <0x020b8000 0x4000>; 531 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&clks IMX6SX_CLK_DUMMY>; 533 status = "disabled"; 534 }; 535 536 wdog1: wdog@020bc000 { 537 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 538 reg = <0x020bc000 0x4000>; 539 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&clks IMX6SX_CLK_DUMMY>; 541 }; 542 543 wdog2: wdog@020c0000 { 544 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 545 reg = <0x020c0000 0x4000>; 546 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&clks IMX6SX_CLK_DUMMY>; 548 status = "disabled"; 549 }; 550 551 clks: ccm@020c4000 { 552 compatible = "fsl,imx6sx-ccm"; 553 reg = <0x020c4000 0x4000>; 554 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 556 #clock-cells = <1>; 557 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; 558 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; 559 }; 560 561 anatop: anatop@020c8000 { 562 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", 563 "syscon", "simple-bus"; 564 reg = <0x020c8000 0x1000>; 565 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 568 569 regulator-1p1 { 570 compatible = "fsl,anatop-regulator"; 571 regulator-name = "vdd1p1"; 572 regulator-min-microvolt = <800000>; 573 regulator-max-microvolt = <1375000>; 574 regulator-always-on; 575 anatop-reg-offset = <0x110>; 576 anatop-vol-bit-shift = <8>; 577 anatop-vol-bit-width = <5>; 578 anatop-min-bit-val = <4>; 579 anatop-min-voltage = <800000>; 580 anatop-max-voltage = <1375000>; 581 }; 582 583 regulator-3p0 { 584 compatible = "fsl,anatop-regulator"; 585 regulator-name = "vdd3p0"; 586 regulator-min-microvolt = <2800000>; 587 regulator-max-microvolt = <3150000>; 588 regulator-always-on; 589 anatop-reg-offset = <0x120>; 590 anatop-vol-bit-shift = <8>; 591 anatop-vol-bit-width = <5>; 592 anatop-min-bit-val = <0>; 593 anatop-min-voltage = <2625000>; 594 anatop-max-voltage = <3400000>; 595 }; 596 597 regulator-2p5 { 598 compatible = "fsl,anatop-regulator"; 599 regulator-name = "vdd2p5"; 600 regulator-min-microvolt = <2100000>; 601 regulator-max-microvolt = <2875000>; 602 regulator-always-on; 603 anatop-reg-offset = <0x130>; 604 anatop-vol-bit-shift = <8>; 605 anatop-vol-bit-width = <5>; 606 anatop-min-bit-val = <0>; 607 anatop-min-voltage = <2100000>; 608 anatop-max-voltage = <2875000>; 609 }; 610 611 reg_arm: regulator-vddcore { 612 compatible = "fsl,anatop-regulator"; 613 regulator-name = "vddarm"; 614 regulator-min-microvolt = <725000>; 615 regulator-max-microvolt = <1450000>; 616 regulator-always-on; 617 anatop-reg-offset = <0x140>; 618 anatop-vol-bit-shift = <0>; 619 anatop-vol-bit-width = <5>; 620 anatop-delay-reg-offset = <0x170>; 621 anatop-delay-bit-shift = <24>; 622 anatop-delay-bit-width = <2>; 623 anatop-min-bit-val = <1>; 624 anatop-min-voltage = <725000>; 625 anatop-max-voltage = <1450000>; 626 }; 627 628 reg_pcie: regulator-vddpcie { 629 compatible = "fsl,anatop-regulator"; 630 regulator-name = "vddpcie"; 631 regulator-min-microvolt = <725000>; 632 regulator-max-microvolt = <1450000>; 633 anatop-reg-offset = <0x140>; 634 anatop-vol-bit-shift = <9>; 635 anatop-vol-bit-width = <5>; 636 anatop-delay-reg-offset = <0x170>; 637 anatop-delay-bit-shift = <26>; 638 anatop-delay-bit-width = <2>; 639 anatop-min-bit-val = <1>; 640 anatop-min-voltage = <725000>; 641 anatop-max-voltage = <1450000>; 642 }; 643 644 reg_soc: regulator-vddsoc { 645 compatible = "fsl,anatop-regulator"; 646 regulator-name = "vddsoc"; 647 regulator-min-microvolt = <725000>; 648 regulator-max-microvolt = <1450000>; 649 regulator-always-on; 650 anatop-reg-offset = <0x140>; 651 anatop-vol-bit-shift = <18>; 652 anatop-vol-bit-width = <5>; 653 anatop-delay-reg-offset = <0x170>; 654 anatop-delay-bit-shift = <28>; 655 anatop-delay-bit-width = <2>; 656 anatop-min-bit-val = <1>; 657 anatop-min-voltage = <725000>; 658 anatop-max-voltage = <1450000>; 659 }; 660 }; 661 662 tempmon: tempmon { 663 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; 664 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 665 fsl,tempmon = <&anatop>; 666 fsl,tempmon-data = <&ocotp>; 667 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; 668 }; 669 670 usbphy1: usbphy@020c9000 { 671 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 672 reg = <0x020c9000 0x1000>; 673 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&clks IMX6SX_CLK_USBPHY1>; 675 fsl,anatop = <&anatop>; 676 }; 677 678 usbphy2: usbphy@020ca000 { 679 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 680 reg = <0x020ca000 0x1000>; 681 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&clks IMX6SX_CLK_USBPHY2>; 683 fsl,anatop = <&anatop>; 684 }; 685 686 snvs: snvs@020cc000 { 687 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 688 reg = <0x020cc000 0x4000>; 689 690 snvs_rtc: snvs-rtc-lp { 691 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 692 regmap = <&snvs>; 693 offset = <0x34>; 694 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 695 }; 696 697 snvs_poweroff: snvs-poweroff { 698 compatible = "syscon-poweroff"; 699 regmap = <&snvs>; 700 offset = <0x38>; 701 mask = <0x60>; 702 status = "disabled"; 703 }; 704 705 snvs_pwrkey: snvs-powerkey { 706 compatible = "fsl,sec-v4.0-pwrkey"; 707 regmap = <&snvs>; 708 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 709 linux,keycode = <KEY_POWER>; 710 wakeup-source; 711 }; 712 }; 713 714 epit1: epit@020d0000 { 715 reg = <0x020d0000 0x4000>; 716 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 717 }; 718 719 epit2: epit@020d4000 { 720 reg = <0x020d4000 0x4000>; 721 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 722 }; 723 724 src: src@020d8000 { 725 compatible = "fsl,imx6sx-src", "fsl,imx51-src"; 726 reg = <0x020d8000 0x4000>; 727 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 729 #reset-cells = <1>; 730 }; 731 732 gpc: gpc@020dc000 { 733 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; 734 reg = <0x020dc000 0x4000>; 735 interrupt-controller; 736 #interrupt-cells = <3>; 737 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 738 interrupt-parent = <&intc>; 739 }; 740 741 iomuxc: iomuxc@020e0000 { 742 compatible = "fsl,imx6sx-iomuxc"; 743 reg = <0x020e0000 0x4000>; 744 }; 745 746 gpr: iomuxc-gpr@020e4000 { 747 compatible = "fsl,imx6sx-iomuxc-gpr", 748 "fsl,imx6q-iomuxc-gpr", "syscon"; 749 reg = <0x020e4000 0x4000>; 750 }; 751 752 sdma: sdma@020ec000 { 753 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; 754 reg = <0x020ec000 0x4000>; 755 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&clks IMX6SX_CLK_SDMA>, 757 <&clks IMX6SX_CLK_SDMA>; 758 clock-names = "ipg", "ahb"; 759 #dma-cells = <3>; 760 /* imx6sx reuses imx6q sdma firmware */ 761 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 762 }; 763 }; 764 765 aips2: aips-bus@02100000 { 766 compatible = "fsl,aips-bus", "simple-bus"; 767 #address-cells = <1>; 768 #size-cells = <1>; 769 reg = <0x02100000 0x100000>; 770 ranges; 771 772 crypto: caam@2100000 { 773 compatible = "fsl,sec-v4.0"; 774 fsl,sec-era = <4>; 775 #address-cells = <1>; 776 #size-cells = <1>; 777 reg = <0x2100000 0x10000>; 778 ranges = <0 0x2100000 0x10000>; 779 interrupt-parent = <&intc>; 780 clocks = <&clks IMX6SX_CLK_CAAM_MEM>, 781 <&clks IMX6SX_CLK_CAAM_ACLK>, 782 <&clks IMX6SX_CLK_CAAM_IPG>, 783 <&clks IMX6SX_CLK_EIM_SLOW>; 784 clock-names = "mem", "aclk", "ipg", "emi_slow"; 785 786 sec_jr0: jr0@1000 { 787 compatible = "fsl,sec-v4.0-job-ring"; 788 reg = <0x1000 0x1000>; 789 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 790 }; 791 792 sec_jr1: jr1@2000 { 793 compatible = "fsl,sec-v4.0-job-ring"; 794 reg = <0x2000 0x1000>; 795 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 796 }; 797 }; 798 799 usbotg1: usb@02184000 { 800 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 801 reg = <0x02184000 0x200>; 802 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&clks IMX6SX_CLK_USBOH3>; 804 fsl,usbphy = <&usbphy1>; 805 fsl,usbmisc = <&usbmisc 0>; 806 fsl,anatop = <&anatop>; 807 ahb-burst-config = <0x0>; 808 tx-burst-size-dword = <0x10>; 809 rx-burst-size-dword = <0x10>; 810 status = "disabled"; 811 }; 812 813 usbotg2: usb@02184200 { 814 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 815 reg = <0x02184200 0x200>; 816 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&clks IMX6SX_CLK_USBOH3>; 818 fsl,usbphy = <&usbphy2>; 819 fsl,usbmisc = <&usbmisc 1>; 820 ahb-burst-config = <0x0>; 821 tx-burst-size-dword = <0x10>; 822 rx-burst-size-dword = <0x10>; 823 status = "disabled"; 824 }; 825 826 usbh: usb@02184400 { 827 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 828 reg = <0x02184400 0x200>; 829 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&clks IMX6SX_CLK_USBOH3>; 831 fsl,usbmisc = <&usbmisc 2>; 832 phy_type = "hsic"; 833 fsl,anatop = <&anatop>; 834 dr_mode = "host"; 835 ahb-burst-config = <0x0>; 836 tx-burst-size-dword = <0x10>; 837 rx-burst-size-dword = <0x10>; 838 status = "disabled"; 839 }; 840 841 usbmisc: usbmisc@02184800 { 842 #index-cells = <1>; 843 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; 844 reg = <0x02184800 0x200>; 845 clocks = <&clks IMX6SX_CLK_USBOH3>; 846 }; 847 848 fec1: ethernet@02188000 { 849 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 850 reg = <0x02188000 0x4000>; 851 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&clks IMX6SX_CLK_ENET>, 854 <&clks IMX6SX_CLK_ENET_AHB>, 855 <&clks IMX6SX_CLK_ENET_PTP>, 856 <&clks IMX6SX_CLK_ENET_REF>, 857 <&clks IMX6SX_CLK_ENET_PTP>; 858 clock-names = "ipg", "ahb", "ptp", 859 "enet_clk_ref", "enet_out"; 860 fsl,num-tx-queues=<3>; 861 fsl,num-rx-queues=<3>; 862 status = "disabled"; 863 }; 864 865 mlb: mlb@0218c000 { 866 reg = <0x0218c000 0x4000>; 867 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&clks IMX6SX_CLK_MLB>; 871 status = "disabled"; 872 }; 873 874 usdhc1: usdhc@02190000 { 875 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 876 reg = <0x02190000 0x4000>; 877 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&clks IMX6SX_CLK_USDHC1>, 879 <&clks IMX6SX_CLK_USDHC1>, 880 <&clks IMX6SX_CLK_USDHC1>; 881 clock-names = "ipg", "ahb", "per"; 882 bus-width = <4>; 883 status = "disabled"; 884 }; 885 886 usdhc2: usdhc@02194000 { 887 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 888 reg = <0x02194000 0x4000>; 889 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&clks IMX6SX_CLK_USDHC2>, 891 <&clks IMX6SX_CLK_USDHC2>, 892 <&clks IMX6SX_CLK_USDHC2>; 893 clock-names = "ipg", "ahb", "per"; 894 bus-width = <4>; 895 status = "disabled"; 896 }; 897 898 usdhc3: usdhc@02198000 { 899 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 900 reg = <0x02198000 0x4000>; 901 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&clks IMX6SX_CLK_USDHC3>, 903 <&clks IMX6SX_CLK_USDHC3>, 904 <&clks IMX6SX_CLK_USDHC3>; 905 clock-names = "ipg", "ahb", "per"; 906 bus-width = <4>; 907 status = "disabled"; 908 }; 909 910 usdhc4: usdhc@0219c000 { 911 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 912 reg = <0x0219c000 0x4000>; 913 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&clks IMX6SX_CLK_USDHC4>, 915 <&clks IMX6SX_CLK_USDHC4>, 916 <&clks IMX6SX_CLK_USDHC4>; 917 clock-names = "ipg", "ahb", "per"; 918 bus-width = <4>; 919 status = "disabled"; 920 }; 921 922 i2c1: i2c@021a0000 { 923 #address-cells = <1>; 924 #size-cells = <0>; 925 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 926 reg = <0x021a0000 0x4000>; 927 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&clks IMX6SX_CLK_I2C1>; 929 status = "disabled"; 930 }; 931 932 i2c2: i2c@021a4000 { 933 #address-cells = <1>; 934 #size-cells = <0>; 935 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 936 reg = <0x021a4000 0x4000>; 937 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&clks IMX6SX_CLK_I2C2>; 939 status = "disabled"; 940 }; 941 942 i2c3: i2c@021a8000 { 943 #address-cells = <1>; 944 #size-cells = <0>; 945 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 946 reg = <0x021a8000 0x4000>; 947 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&clks IMX6SX_CLK_I2C3>; 949 status = "disabled"; 950 }; 951 952 mmdc: mmdc@021b0000 { 953 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; 954 reg = <0x021b0000 0x4000>; 955 }; 956 957 fec2: ethernet@021b4000 { 958 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 959 reg = <0x021b4000 0x4000>; 960 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&clks IMX6SX_CLK_ENET>, 963 <&clks IMX6SX_CLK_ENET_AHB>, 964 <&clks IMX6SX_CLK_ENET_PTP>, 965 <&clks IMX6SX_CLK_ENET2_REF_125M>, 966 <&clks IMX6SX_CLK_ENET_PTP>; 967 clock-names = "ipg", "ahb", "ptp", 968 "enet_clk_ref", "enet_out"; 969 status = "disabled"; 970 }; 971 972 weim: weim@021b8000 { 973 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; 974 reg = <0x021b8000 0x4000>; 975 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&clks IMX6SX_CLK_EIM_SLOW>; 977 }; 978 979 ocotp: ocotp@021bc000 { 980 compatible = "fsl,imx6sx-ocotp", "syscon"; 981 reg = <0x021bc000 0x4000>; 982 clocks = <&clks IMX6SX_CLK_OCOTP>; 983 }; 984 985 sai1: sai@021d4000 { 986 compatible = "fsl,imx6sx-sai"; 987 reg = <0x021d4000 0x4000>; 988 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&clks IMX6SX_CLK_SAI1_IPG>, 990 <&clks IMX6SX_CLK_SAI1>, 991 <&clks 0>, <&clks 0>; 992 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 993 dma-names = "rx", "tx"; 994 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; 995 status = "disabled"; 996 }; 997 998 audmux: audmux@021d8000 { 999 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; 1000 reg = <0x021d8000 0x4000>; 1001 status = "disabled"; 1002 }; 1003 1004 sai2: sai@021dc000 { 1005 compatible = "fsl,imx6sx-sai"; 1006 reg = <0x021dc000 0x4000>; 1007 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&clks IMX6SX_CLK_SAI2_IPG>, 1009 <&clks IMX6SX_CLK_SAI2>, 1010 <&clks 0>, <&clks 0>; 1011 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1012 dma-names = "rx", "tx"; 1013 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; 1014 status = "disabled"; 1015 }; 1016 1017 qspi1: qspi@021e0000 { 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 compatible = "fsl,imx6sx-qspi"; 1021 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 1022 reg-names = "QuadSPI", "QuadSPI-memory"; 1023 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1024 clocks = <&clks IMX6SX_CLK_QSPI1>, 1025 <&clks IMX6SX_CLK_QSPI1>; 1026 clock-names = "qspi_en", "qspi"; 1027 status = "disabled"; 1028 }; 1029 1030 qspi2: qspi@021e4000 { 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 compatible = "fsl,imx6sx-qspi"; 1034 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; 1035 reg-names = "QuadSPI", "QuadSPI-memory"; 1036 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&clks IMX6SX_CLK_QSPI2>, 1038 <&clks IMX6SX_CLK_QSPI2>; 1039 clock-names = "qspi_en", "qspi"; 1040 status = "disabled"; 1041 }; 1042 1043 uart2: serial@021e8000 { 1044 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; 1045 reg = <0x021e8000 0x4000>; 1046 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1048 <&clks IMX6SX_CLK_UART_SERIAL>; 1049 clock-names = "ipg", "per"; 1050 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1051 dma-names = "rx", "tx"; 1052 status = "disabled"; 1053 }; 1054 1055 uart3: serial@021ec000 { 1056 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; 1057 reg = <0x021ec000 0x4000>; 1058 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1060 <&clks IMX6SX_CLK_UART_SERIAL>; 1061 clock-names = "ipg", "per"; 1062 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1063 dma-names = "rx", "tx"; 1064 status = "disabled"; 1065 }; 1066 1067 uart4: serial@021f0000 { 1068 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; 1069 reg = <0x021f0000 0x4000>; 1070 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1072 <&clks IMX6SX_CLK_UART_SERIAL>; 1073 clock-names = "ipg", "per"; 1074 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1075 dma-names = "rx", "tx"; 1076 status = "disabled"; 1077 }; 1078 1079 uart5: serial@021f4000 { 1080 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; 1081 reg = <0x021f4000 0x4000>; 1082 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1084 <&clks IMX6SX_CLK_UART_SERIAL>; 1085 clock-names = "ipg", "per"; 1086 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1087 dma-names = "rx", "tx"; 1088 status = "disabled"; 1089 }; 1090 1091 i2c4: i2c@021f8000 { 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1095 reg = <0x021f8000 0x4000>; 1096 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&clks IMX6SX_CLK_I2C4>; 1098 status = "disabled"; 1099 }; 1100 }; 1101 1102 aips3: aips-bus@02200000 { 1103 compatible = "fsl,aips-bus", "simple-bus"; 1104 #address-cells = <1>; 1105 #size-cells = <1>; 1106 reg = <0x02200000 0x100000>; 1107 ranges; 1108 1109 spba-bus@02200000 { 1110 compatible = "fsl,spba-bus", "simple-bus"; 1111 #address-cells = <1>; 1112 #size-cells = <1>; 1113 reg = <0x02240000 0x40000>; 1114 ranges; 1115 1116 csi1: csi@02214000 { 1117 reg = <0x02214000 0x4000>; 1118 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1120 <&clks IMX6SX_CLK_CSI>, 1121 <&clks IMX6SX_CLK_DCIC1>; 1122 clock-names = "disp-axi", "csi_mclk", "dcic"; 1123 status = "disabled"; 1124 }; 1125 1126 pxp: pxp@02218000 { 1127 reg = <0x02218000 0x4000>; 1128 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&clks IMX6SX_CLK_PXP_AXI>, 1130 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1131 clock-names = "pxp-axi", "disp-axi"; 1132 status = "disabled"; 1133 }; 1134 1135 csi2: csi@0221c000 { 1136 reg = <0x0221c000 0x4000>; 1137 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1139 <&clks IMX6SX_CLK_CSI>, 1140 <&clks IMX6SX_CLK_DCIC2>; 1141 clock-names = "disp-axi", "csi_mclk", "dcic"; 1142 status = "disabled"; 1143 }; 1144 1145 lcdif1: lcdif@02220000 { 1146 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1147 reg = <0x02220000 0x4000>; 1148 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, 1150 <&clks IMX6SX_CLK_LCDIF_APB>, 1151 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1152 clock-names = "pix", "axi", "disp_axi"; 1153 status = "disabled"; 1154 }; 1155 1156 lcdif2: lcdif@02224000 { 1157 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1158 reg = <0x02224000 0x4000>; 1159 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, 1161 <&clks IMX6SX_CLK_LCDIF_APB>, 1162 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1163 clock-names = "pix", "axi", "disp_axi"; 1164 status = "disabled"; 1165 }; 1166 1167 vadc: vadc@02228000 { 1168 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; 1169 reg-names = "vadc-vafe", "vadc-vdec"; 1170 clocks = <&clks IMX6SX_CLK_VADC>, 1171 <&clks IMX6SX_CLK_CSI>; 1172 clock-names = "vadc", "csi"; 1173 status = "disabled"; 1174 }; 1175 }; 1176 1177 adc1: adc@02280000 { 1178 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1179 reg = <0x02280000 0x4000>; 1180 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1181 clocks = <&clks IMX6SX_CLK_IPG>; 1182 clock-names = "adc"; 1183 fsl,adck-max-frequency = <30000000>, <40000000>, 1184 <20000000>; 1185 status = "disabled"; 1186 }; 1187 1188 adc2: adc@02284000 { 1189 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1190 reg = <0x02284000 0x4000>; 1191 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1192 clocks = <&clks IMX6SX_CLK_IPG>; 1193 clock-names = "adc"; 1194 fsl,adck-max-frequency = <30000000>, <40000000>, 1195 <20000000>; 1196 status = "disabled"; 1197 }; 1198 1199 wdog3: wdog@02288000 { 1200 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 1201 reg = <0x02288000 0x4000>; 1202 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&clks IMX6SX_CLK_DUMMY>; 1204 status = "disabled"; 1205 }; 1206 1207 ecspi5: ecspi@0228c000 { 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 1211 reg = <0x0228c000 0x4000>; 1212 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1213 clocks = <&clks IMX6SX_CLK_ECSPI5>, 1214 <&clks IMX6SX_CLK_ECSPI5>; 1215 clock-names = "ipg", "per"; 1216 status = "disabled"; 1217 }; 1218 1219 uart6: serial@022a0000 { 1220 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; 1221 reg = <0x022a0000 0x4000>; 1222 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1224 <&clks IMX6SX_CLK_UART_SERIAL>; 1225 clock-names = "ipg", "per"; 1226 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; 1227 dma-names = "rx", "tx"; 1228 status = "disabled"; 1229 }; 1230 1231 pwm5: pwm@022a4000 { 1232 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1233 reg = <0x022a4000 0x4000>; 1234 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&clks IMX6SX_CLK_PWM5>, 1236 <&clks IMX6SX_CLK_PWM5>; 1237 clock-names = "ipg", "per"; 1238 #pwm-cells = <2>; 1239 }; 1240 1241 pwm6: pwm@022a8000 { 1242 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1243 reg = <0x022a8000 0x4000>; 1244 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&clks IMX6SX_CLK_PWM6>, 1246 <&clks IMX6SX_CLK_PWM6>; 1247 clock-names = "ipg", "per"; 1248 #pwm-cells = <2>; 1249 }; 1250 1251 pwm7: pwm@022ac000 { 1252 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1253 reg = <0x022ac000 0x4000>; 1254 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&clks IMX6SX_CLK_PWM7>, 1256 <&clks IMX6SX_CLK_PWM7>; 1257 clock-names = "ipg", "per"; 1258 #pwm-cells = <2>; 1259 }; 1260 1261 pwm8: pwm@0022b0000 { 1262 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1263 reg = <0x0022b0000 0x4000>; 1264 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1265 clocks = <&clks IMX6SX_CLK_PWM8>, 1266 <&clks IMX6SX_CLK_PWM8>; 1267 clock-names = "ipg", "per"; 1268 #pwm-cells = <2>; 1269 }; 1270 }; 1271 1272 pcie: pcie@0x08000000 { 1273 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; 1274 reg = <0x08ffc000 0x4000>; /* DBI */ 1275 #address-cells = <3>; 1276 #size-cells = <2>; 1277 device_type = "pci"; 1278 /* configuration space */ 1279 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 1280 /* downstream I/O */ 1281 0x81000000 0 0 0x08f80000 0 0x00010000 1282 /* non-prefetchable memory */ 1283 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; 1284 num-lanes = <1>; 1285 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1286 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, 1287 <&clks IMX6SX_CLK_PCIE_AXI>, 1288 <&clks IMX6SX_CLK_LVDS1_OUT>, 1289 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1290 clock-names = "pcie_ref_125m", "pcie_axi", 1291 "lvds_gate", "display_axi"; 1292 status = "disabled"; 1293 }; 1294 }; 1295 1296 gpu-subsystem { 1297 compatible = "fsl,imx-gpu-subsystem"; 1298 cores = <&gpu>; 1299 }; 1300}; 1301