1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/input.h>
8
9/ {
10	chosen {
11		stdout-path = &uart4;
12	};
13
14	memory@10000000 {
15		reg = <0x10000000 0x80000000>;
16	};
17
18	leds {
19		compatible = "gpio-leds";
20		pinctrl-names = "default";
21		pinctrl-0 = <&pinctrl_gpio_leds>;
22
23		user {
24			label = "debug";
25			gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
26		};
27	};
28
29	gpio-keys {
30		compatible = "gpio-keys";
31		pinctrl-names = "default";
32		pinctrl-0 = <&pinctrl_gpio_keys>;
33
34		home {
35			label = "Home";
36			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
37			linux,code = <KEY_HOME>;
38			wakeup-source;
39		};
40
41		back {
42			label = "Back";
43			gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
44			linux,code = <KEY_BACK>;
45			wakeup-source;
46		};
47
48		program {
49			label = "Program";
50			gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
51			linux,code = <KEY_PROGRAM>;
52			wakeup-source;
53		};
54
55		volume-up {
56			label = "Volume Up";
57			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
58			linux,code = <KEY_VOLUMEUP>;
59			wakeup-source;
60		};
61
62		volume-down {
63			label = "Volume Down";
64			gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
65			linux,code = <KEY_VOLUMEDOWN>;
66			wakeup-source;
67		};
68	};
69
70	clocks {
71		codec_osc: anaclk2 {
72			compatible = "fixed-clock";
73			#clock-cells = <0>;
74			clock-frequency = <24576000>;
75		};
76	};
77
78	regulators {
79		compatible = "simple-bus";
80		#address-cells = <1>;
81		#size-cells = <0>;
82
83		reg_audio: regulator@0 {
84			compatible = "regulator-fixed";
85			reg = <0>;
86			regulator-name = "cs42888_supply";
87			regulator-min-microvolt = <3300000>;
88			regulator-max-microvolt = <3300000>;
89			regulator-always-on;
90		};
91
92		reg_usb_h1_vbus: regulator@1 {
93			compatible = "regulator-fixed";
94			reg = <1>;
95			regulator-name = "usb_h1_vbus";
96			regulator-min-microvolt = <5000000>;
97			regulator-max-microvolt = <5000000>;
98			gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
99			enable-active-high;
100		};
101
102		reg_usb_otg_vbus: regulator@2 {
103			compatible = "regulator-fixed";
104			reg = <2>;
105			regulator-name = "usb_otg_vbus";
106			regulator-min-microvolt = <5000000>;
107			regulator-max-microvolt = <5000000>;
108			gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
109			enable-active-high;
110		};
111	};
112
113	sound-cs42888 {
114		compatible = "fsl,imx6-sabreauto-cs42888",
115			"fsl,imx-audio-cs42888";
116		model = "imx-cs42888";
117		audio-cpu = <&esai>;
118		audio-asrc = <&asrc>;
119		audio-codec = <&codec>;
120		audio-routing =
121			"Line Out Jack", "AOUT1L",
122			"Line Out Jack", "AOUT1R",
123			"Line Out Jack", "AOUT2L",
124			"Line Out Jack", "AOUT2R",
125			"Line Out Jack", "AOUT3L",
126			"Line Out Jack", "AOUT3R",
127			"Line Out Jack", "AOUT4L",
128			"Line Out Jack", "AOUT4R",
129			"AIN1L", "Line In Jack",
130			"AIN1R", "Line In Jack",
131			"AIN2L", "Line In Jack",
132			"AIN2R", "Line In Jack";
133	};
134
135	sound-spdif {
136		compatible = "fsl,imx-audio-spdif",
137			   "fsl,imx-sabreauto-spdif";
138		model = "imx-spdif";
139		spdif-controller = <&spdif>;
140		spdif-in;
141	};
142
143	backlight {
144		compatible = "pwm-backlight";
145		pwms = <&pwm3 0 5000000>;
146		brightness-levels = <0 4 8 16 32 64 128 255>;
147		default-brightness-level = <7>;
148		status = "okay";
149	};
150
151	i2cmux {
152		compatible = "i2c-mux-gpio";
153		#address-cells = <1>;
154		#size-cells = <0>;
155		pinctrl-names = "default";
156		pinctrl-0 = <&pinctrl_i2c3mux>;
157		mux-gpios = <&gpio5 4 0>;
158		i2c-parent = <&i2c3>;
159		idle-state = <0>;
160
161		i2c@1 {
162			#address-cells = <1>;
163			#size-cells = <0>;
164			reg = <1>;
165
166			adv7180: camera@21 {
167				compatible = "adi,adv7180";
168				reg = <0x21>;
169				powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
170				interrupt-parent = <&gpio1>;
171				interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
172
173				port {
174					adv7180_to_ipu1_csi0_mux: endpoint {
175						remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
176						bus-width = <8>;
177					};
178				};
179			};
180
181			max7310_a: gpio@30 {
182				compatible = "maxim,max7310";
183				reg = <0x30>;
184				gpio-controller;
185				#gpio-cells = <2>;
186			};
187
188			max7310_b: gpio@32 {
189				compatible = "maxim,max7310";
190				reg = <0x32>;
191				gpio-controller;
192				#gpio-cells = <2>;
193				pinctrl-names = "default";
194				pinctrl-0 = <&pinctrl_max7310>;
195				reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
196			};
197
198			max7310_c: gpio@34 {
199				compatible = "maxim,max7310";
200				reg = <0x34>;
201				gpio-controller;
202				#gpio-cells = <2>;
203			};
204
205			light-sensor@44 {
206				compatible = "isil,isl29023";
207				reg = <0x44>;
208				interrupt-parent = <&gpio5>;
209				interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
210			};
211
212			magnetometer@e {
213				compatible = "fsl,mag3110";
214				reg = <0x0e>;
215				interrupt-parent = <&gpio2>;
216				interrupts = <29 IRQ_TYPE_EDGE_RISING>;
217			};
218
219			accelerometer@1c {
220				compatible = "fsl,mma8451";
221				reg = <0x1c>;
222				interrupt-parent = <&gpio6>;
223				interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
224			};
225		};
226	};
227};
228
229&ipu1_csi0_from_ipu1_csi0_mux {
230	bus-width = <8>;
231};
232
233&ipu1_csi0_mux_from_parallel_sensor {
234	remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
235	bus-width = <8>;
236};
237
238&ipu1_csi0 {
239	pinctrl-names = "default";
240	pinctrl-0 = <&pinctrl_ipu1_csi0>;
241};
242
243&clks {
244	assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
245			  <&clks IMX6QDL_PLL4_BYPASS>,
246			  <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
247			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
248			  <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
249	assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
250				 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
251				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
252				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
253	assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
254};
255
256&ecspi1 {
257	cs-gpios = <&gpio3 19 0>;
258	pinctrl-names = "default";
259	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
260	status = "disabled"; /* pin conflict with WEIM NOR */
261
262	flash: m25p80@0 {
263		#address-cells = <1>;
264		#size-cells = <1>;
265		compatible = "st,m25p32", "jedec,spi-nor";
266		spi-max-frequency = <20000000>;
267		reg = <0>;
268	};
269};
270
271&esai {
272	pinctrl-names = "default";
273	pinctrl-0 = <&pinctrl_esai>;
274	assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
275			  <&clks IMX6QDL_CLK_ESAI_EXTAL>;
276	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
277	assigned-clock-rates = <0>, <24576000>;
278	status = "okay";
279};
280
281&fec {
282	pinctrl-names = "default";
283	pinctrl-0 = <&pinctrl_enet>;
284	phy-mode = "rgmii";
285	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
286			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
287	fsl,err006687-workaround-present;
288	status = "okay";
289};
290
291&gpmi {
292	pinctrl-names = "default";
293	pinctrl-0 = <&pinctrl_gpmi_nand>;
294	status = "okay";
295};
296
297&hdmi {
298	pinctrl-names = "default";
299	pinctrl-0 = <&pinctrl_hdmi_cec>;
300	ddc-i2c-bus = <&i2c2>;
301	status = "okay";
302};
303
304&i2c2 {
305	clock-frequency = <100000>;
306	pinctrl-names = "default";
307	pinctrl-0 = <&pinctrl_i2c2>;
308	status = "okay";
309
310	pmic: pfuze100@8 {
311		compatible = "fsl,pfuze100";
312		reg = <0x08>;
313
314		regulators {
315			sw1a_reg: sw1ab {
316				regulator-min-microvolt = <300000>;
317				regulator-max-microvolt = <1875000>;
318				regulator-boot-on;
319				regulator-always-on;
320				regulator-ramp-delay = <6250>;
321			};
322
323			sw1c_reg: sw1c {
324				regulator-min-microvolt = <300000>;
325				regulator-max-microvolt = <1875000>;
326				regulator-boot-on;
327				regulator-always-on;
328				regulator-ramp-delay = <6250>;
329			};
330
331			sw2_reg: sw2 {
332				regulator-min-microvolt = <800000>;
333				regulator-max-microvolt = <3300000>;
334				regulator-boot-on;
335				regulator-always-on;
336			};
337
338			sw3a_reg: sw3a {
339				regulator-min-microvolt = <400000>;
340				regulator-max-microvolt = <1975000>;
341				regulator-boot-on;
342				regulator-always-on;
343			};
344
345			sw3b_reg: sw3b {
346				regulator-min-microvolt = <400000>;
347				regulator-max-microvolt = <1975000>;
348				regulator-boot-on;
349				regulator-always-on;
350			};
351
352			sw4_reg: sw4 {
353				regulator-min-microvolt = <800000>;
354				regulator-max-microvolt = <3300000>;
355			};
356
357			swbst_reg: swbst {
358				regulator-min-microvolt = <5000000>;
359				regulator-max-microvolt = <5150000>;
360			};
361
362			snvs_reg: vsnvs {
363				regulator-min-microvolt = <1000000>;
364				regulator-max-microvolt = <3000000>;
365				regulator-boot-on;
366				regulator-always-on;
367			};
368
369			vref_reg: vrefddr {
370				regulator-boot-on;
371				regulator-always-on;
372			};
373
374			vgen1_reg: vgen1 {
375				regulator-min-microvolt = <800000>;
376				regulator-max-microvolt = <1550000>;
377			};
378
379			vgen2_reg: vgen2 {
380				regulator-min-microvolt = <800000>;
381				regulator-max-microvolt = <1550000>;
382			};
383
384			vgen3_reg: vgen3 {
385				regulator-min-microvolt = <1800000>;
386				regulator-max-microvolt = <3300000>;
387			};
388
389			vgen4_reg: vgen4 {
390				regulator-min-microvolt = <1800000>;
391				regulator-max-microvolt = <3300000>;
392				regulator-always-on;
393			};
394
395			vgen5_reg: vgen5 {
396				regulator-min-microvolt = <1800000>;
397				regulator-max-microvolt = <3300000>;
398				regulator-always-on;
399			};
400
401			vgen6_reg: vgen6 {
402				regulator-min-microvolt = <1800000>;
403				regulator-max-microvolt = <3300000>;
404				regulator-always-on;
405			};
406		};
407	};
408
409	codec: cs42888@48 {
410		compatible = "cirrus,cs42888";
411		reg = <0x48>;
412		clocks = <&codec_osc>;
413		clock-names = "mclk";
414		VA-supply = <&reg_audio>;
415		VD-supply = <&reg_audio>;
416		VLS-supply = <&reg_audio>;
417		VLC-supply = <&reg_audio>;
418	};
419
420	touchscreen@4 {
421		compatible = "eeti,egalax_ts";
422		reg = <0x04>;
423		pinctrl-names = "default";
424		pinctrl-0 = <&pinctrl_egalax_int>;
425		interrupt-parent = <&gpio2>;
426		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
427		wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
428	};
429};
430
431&i2c3 {
432	pinctrl-names = "default";
433	pinctrl-0 = <&pinctrl_i2c3>;
434	status = "okay";
435};
436
437&iomuxc {
438	pinctrl-names = "default";
439	pinctrl-0 = <&pinctrl_hog>;
440
441	imx6qdl-sabreauto {
442		pinctrl_hog: hoggrp {
443			fsl,pins = <
444				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
445				MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
446				MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
447			>;
448		};
449
450		pinctrl_ecspi1: ecspi1grp {
451			fsl,pins = <
452				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
453				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
454				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
455			>;
456		};
457
458		pinctrl_ecspi1_cs: ecspi1cs {
459			fsl,pins = <
460				MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
461			>;
462		};
463
464		pinctrl_egalax_int: egalax-intgrp {
465			fsl,pins = <
466				MX6QDL_PAD_EIM_EB0__GPIO2_IO28		0xb0b1
467			>;
468		};
469
470		pinctrl_enet: enetgrp {
471			fsl,pins = <
472				MX6QDL_PAD_KEY_COL1__ENET_MDIO		0x1b0b0
473				MX6QDL_PAD_KEY_COL2__ENET_MDC		0x1b0b0
474				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
475				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
476				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
477				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
478				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
479				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
480				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
481				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
482				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
483				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
484				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
485				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
486				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
487				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
488			>;
489		};
490
491		pinctrl_esai: esaigrp {
492			fsl,pins = <
493				MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
494				MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
495				MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
496				MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
497				MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
498				MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
499				MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
500				MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
501				MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
502				MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
503			>;
504		};
505
506		pinctrl_gpio_keys: gpiokeysgrp {
507			fsl,pins = <
508				MX6QDL_PAD_SD2_CMD__GPIO1_IO11		0x1b0b0
509				MX6QDL_PAD_SD2_DAT3__GPIO1_IO12		0x1b0b0
510				MX6QDL_PAD_SD4_DAT4__GPIO2_IO12		0x1b0b0
511				MX6QDL_PAD_SD4_DAT7__GPIO2_IO15		0x1b0b0
512				MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14	0x1b0b0
513			>;
514		};
515
516		pinctrl_gpio_leds: gpioledsgrp {
517			fsl,pins = <
518				MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15	0x80000000
519			>;
520		};
521
522		pinctrl_gpmi_nand: gpminandgrp {
523			fsl,pins = <
524				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
525				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
526				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
527				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
528				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
529				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
530				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
531				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
532				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
533				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
534				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
535				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
536				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
537				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
538				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
539				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
540				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
541			>;
542		};
543
544		pinctrl_hdmi_cec: hdmicecgrp {
545			fsl,pins = <
546				MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE	0x1f8b0
547			>;
548		};
549
550		pinctrl_i2c2: i2c2grp {
551			fsl,pins = <
552				MX6QDL_PAD_EIM_EB2__I2C2_SCL	0x4001b8b1
553				MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
554			>;
555		};
556
557		pinctrl_i2c3: i2c3grp {
558			fsl,pins = <
559				MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
560				MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
561			>;
562		};
563
564		pinctrl_i2c3mux: i2c3muxgrp {
565			fsl,pins = <
566				MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
567			>;
568		};
569
570		pinctrl_ipu1_csi0: ipu1csi0grp {
571			fsl,pins = <
572				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x1b0b0
573				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x1b0b0
574				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x1b0b0
575				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x1b0b0
576				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x1b0b0
577				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x1b0b0
578				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x1b0b0
579				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x1b0b0
580				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
581				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x1b0b0
582				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x1b0b0
583			>;
584		};
585
586		pinctrl_max7310: max7310grp {
587			fsl,pins = <
588				MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
589			>;
590		};
591
592		pinctrl_pwm3: pwm1grp {
593			fsl,pins = <
594				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
595			>;
596		};
597
598		pinctrl_gpt_input_capture0: gptinputcapture0grp {
599			fsl,pins = <
600				MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1	0x1b0b0
601			>;
602		};
603
604		pinctrl_gpt_input_capture1: gptinputcapture1grp {
605			fsl,pins = <
606				MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2	0x1b0b0
607			>;
608		};
609
610		pinctrl_spdif: spdifgrp {
611			fsl,pins = <
612				MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
613			>;
614		};
615
616		pinctrl_uart4: uart4grp {
617			fsl,pins = <
618				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
619				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
620			>;
621		};
622
623		pinctrl_usbotg: usbotggrp {
624			fsl,pins = <
625				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
626			>;
627		};
628
629		pinctrl_usdhc3: usdhc3grp {
630			fsl,pins = <
631				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
632				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
633				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
634				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
635				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
636				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
637				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
638				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
639				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
640				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
641			>;
642		};
643
644		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
645			fsl,pins = <
646				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
647				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
648				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
649				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
650				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
651				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
652				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170b9
653				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170b9
654				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170b9
655				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170b9
656			>;
657		};
658
659		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
660			fsl,pins = <
661				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
662				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
663				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
664				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
665				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
666				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
667				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170f9
668				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170f9
669				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170f9
670				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170f9
671			>;
672		};
673
674		pinctrl_weim_cs0: weimcs0grp {
675			fsl,pins = <
676				MX6QDL_PAD_EIM_CS0__EIM_CS0_B		0xb0b1
677			>;
678		};
679
680		pinctrl_weim_nor: weimnorgrp {
681			fsl,pins = <
682				MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0b1
683				MX6QDL_PAD_EIM_RW__EIM_RW		0xb0b1
684				MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B		0xb060
685				MX6QDL_PAD_EIM_D16__EIM_DATA16		0x1b0b0
686				MX6QDL_PAD_EIM_D17__EIM_DATA17		0x1b0b0
687				MX6QDL_PAD_EIM_D18__EIM_DATA18		0x1b0b0
688				MX6QDL_PAD_EIM_D19__EIM_DATA19		0x1b0b0
689				MX6QDL_PAD_EIM_D20__EIM_DATA20		0x1b0b0
690				MX6QDL_PAD_EIM_D21__EIM_DATA21		0x1b0b0
691				MX6QDL_PAD_EIM_D22__EIM_DATA22		0x1b0b0
692				MX6QDL_PAD_EIM_D23__EIM_DATA23		0x1b0b0
693				MX6QDL_PAD_EIM_D24__EIM_DATA24		0x1b0b0
694				MX6QDL_PAD_EIM_D25__EIM_DATA25		0x1b0b0
695				MX6QDL_PAD_EIM_D26__EIM_DATA26		0x1b0b0
696				MX6QDL_PAD_EIM_D27__EIM_DATA27		0x1b0b0
697				MX6QDL_PAD_EIM_D28__EIM_DATA28		0x1b0b0
698				MX6QDL_PAD_EIM_D29__EIM_DATA29		0x1b0b0
699				MX6QDL_PAD_EIM_D30__EIM_DATA30		0x1b0b0
700				MX6QDL_PAD_EIM_D31__EIM_DATA31		0x1b0b0
701				MX6QDL_PAD_EIM_A23__EIM_ADDR23		0xb0b1
702				MX6QDL_PAD_EIM_A22__EIM_ADDR22		0xb0b1
703				MX6QDL_PAD_EIM_A21__EIM_ADDR21		0xb0b1
704				MX6QDL_PAD_EIM_A20__EIM_ADDR20		0xb0b1
705				MX6QDL_PAD_EIM_A19__EIM_ADDR19		0xb0b1
706				MX6QDL_PAD_EIM_A18__EIM_ADDR18		0xb0b1
707				MX6QDL_PAD_EIM_A17__EIM_ADDR17		0xb0b1
708				MX6QDL_PAD_EIM_A16__EIM_ADDR16		0xb0b1
709				MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0b1
710				MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0b1
711				MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0b1
712				MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0b1
713				MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0b1
714				MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0b1
715				MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0b1
716				MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0b1
717				MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0b1
718				MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0b1
719				MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0b1
720				MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0b1
721				MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0b1
722				MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0b1
723				MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0b1
724				MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0b1
725			>;
726		};
727	};
728};
729
730&ldb {
731	status = "okay";
732
733	lvds-channel@0 {
734		fsl,data-mapping = "spwg";
735		fsl,data-width = <18>;
736		status = "okay";
737
738		display-timings {
739			native-mode = <&timing0>;
740			timing0: hsd100pxn1 {
741				clock-frequency = <65000000>;
742				hactive = <1024>;
743				vactive = <768>;
744				hback-porch = <220>;
745				hfront-porch = <40>;
746				vback-porch = <21>;
747				vfront-porch = <7>;
748				hsync-len = <60>;
749				vsync-len = <10>;
750			};
751		};
752	};
753};
754
755&pwm3 {
756	pinctrl-names = "default";
757	pinctrl-0 = <&pinctrl_pwm3>;
758	status = "okay";
759};
760
761&spdif {
762	pinctrl-names = "default";
763	pinctrl-0 = <&pinctrl_spdif>;
764	status = "okay";
765};
766
767&uart4 {
768	pinctrl-names = "default";
769	pinctrl-0 = <&pinctrl_uart4>;
770	status = "okay";
771};
772
773&usbh1 {
774	vbus-supply = <&reg_usb_h1_vbus>;
775	status = "okay";
776};
777
778&usbotg {
779	vbus-supply = <&reg_usb_otg_vbus>;
780	pinctrl-names = "default";
781	pinctrl-0 = <&pinctrl_usbotg>;
782	status = "okay";
783};
784
785&usdhc3 {
786	pinctrl-names = "default", "state_100mhz", "state_200mhz";
787	pinctrl-0 = <&pinctrl_usdhc3>;
788	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
789	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
790	cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
791	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
792	status = "okay";
793};
794
795&weim {
796	pinctrl-names = "default";
797	pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
798	ranges = <0 0 0x08000000 0x08000000>;
799	status = "disabled"; /* pin conflict with SPI NOR */
800
801	nor@0,0 {
802		compatible = "cfi-flash";
803		reg = <0 0 0x02000000>;
804		#address-cells = <1>;
805		#size-cells = <1>;
806		bank-width = <2>;
807		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
808				0x0000c000 0x1404a38e 0x00000000>;
809	};
810};
811