1/* 2 * DTS File for HiSilicon Hi3798cv200 SoC. 3 * 4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. 5 * 6 * Released under the GPLv2 only. 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10#include <dt-bindings/clock/histb-clock.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/ti-syscon.h> 13 14/ { 15 compatible = "hisilicon,hi3798cv200"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 psci { 21 compatible = "arm,psci-0.2"; 22 method = "smc"; 23 }; 24 25 cpus { 26 #address-cells = <2>; 27 #size-cells = <0>; 28 29 cpu@0 { 30 compatible = "arm,cortex-a53"; 31 device_type = "cpu"; 32 reg = <0x0 0x0>; 33 enable-method = "psci"; 34 }; 35 36 cpu@1 { 37 compatible = "arm,cortex-a53"; 38 device_type = "cpu"; 39 reg = <0x0 0x1>; 40 enable-method = "psci"; 41 }; 42 43 cpu@2 { 44 compatible = "arm,cortex-a53"; 45 device_type = "cpu"; 46 reg = <0x0 0x2>; 47 enable-method = "psci"; 48 }; 49 50 cpu@3 { 51 compatible = "arm,cortex-a53"; 52 device_type = "cpu"; 53 reg = <0x0 0x3>; 54 enable-method = "psci"; 55 }; 56 }; 57 58 gic: interrupt-controller@f1001000 { 59 compatible = "arm,gic-400"; 60 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ 61 <0x0 0xf1002000 0x0 0x100>; /* GICC */ 62 #address-cells = <0>; 63 #interrupt-cells = <3>; 64 interrupt-controller; 65 }; 66 67 timer { 68 compatible = "arm,armv8-timer"; 69 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 70 IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 72 IRQ_TYPE_LEVEL_LOW)>, 73 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 74 IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 76 IRQ_TYPE_LEVEL_LOW)>; 77 }; 78 79 soc: soc@f0000000 { 80 compatible = "simple-bus"; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0x0 0x0 0xf0000000 0x10000000>; 84 85 crg: clock-reset-controller@8a22000 { 86 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; 87 reg = <0x8a22000 0x1000>; 88 #clock-cells = <1>; 89 #reset-cells = <2>; 90 91 gmacphyrst: reset-controller { 92 compatible = "ti,syscon-reset"; 93 #reset-cells = <1>; 94 ti,reset-bits = 95 <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | 96 DEASSERT_SET|STATUS_NONE)>, 97 <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | 98 DEASSERT_SET|STATUS_NONE)>; 99 }; 100 }; 101 102 sysctrl: system-controller@8000000 { 103 compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; 104 reg = <0x8000000 0x1000>; 105 #clock-cells = <1>; 106 #reset-cells = <2>; 107 }; 108 109 uart0: serial@8b00000 { 110 compatible = "arm,pl011", "arm,primecell"; 111 reg = <0x8b00000 0x1000>; 112 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 113 clocks = <&sysctrl HISTB_UART0_CLK>; 114 clock-names = "apb_pclk"; 115 status = "disabled"; 116 }; 117 118 uart2: serial@8b02000 { 119 compatible = "arm,pl011", "arm,primecell"; 120 reg = <0x8b02000 0x1000>; 121 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 122 clocks = <&crg HISTB_UART2_CLK>; 123 clock-names = "apb_pclk"; 124 status = "disabled"; 125 }; 126 127 i2c0: i2c@8b10000 { 128 compatible = "hisilicon,hix5hd2-i2c"; 129 reg = <0x8b10000 0x1000>; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 133 clock-frequency = <400000>; 134 clocks = <&crg HISTB_I2C0_CLK>; 135 status = "disabled"; 136 }; 137 138 i2c1: i2c@8b11000 { 139 compatible = "hisilicon,hix5hd2-i2c"; 140 reg = <0x8b11000 0x1000>; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 144 clock-frequency = <400000>; 145 clocks = <&crg HISTB_I2C1_CLK>; 146 status = "disabled"; 147 }; 148 149 i2c2: i2c@8b12000 { 150 compatible = "hisilicon,hix5hd2-i2c"; 151 reg = <0x8b12000 0x1000>; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 155 clock-frequency = <400000>; 156 clocks = <&crg HISTB_I2C2_CLK>; 157 status = "disabled"; 158 }; 159 160 i2c3: i2c@8b13000 { 161 compatible = "hisilicon,hix5hd2-i2c"; 162 reg = <0x8b13000 0x1000>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 166 clock-frequency = <400000>; 167 clocks = <&crg HISTB_I2C3_CLK>; 168 status = "disabled"; 169 }; 170 171 i2c4: i2c@8b14000 { 172 compatible = "hisilicon,hix5hd2-i2c"; 173 reg = <0x8b14000 0x1000>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 177 clock-frequency = <400000>; 178 clocks = <&crg HISTB_I2C4_CLK>; 179 status = "disabled"; 180 }; 181 182 spi0: spi@8b1a000 { 183 compatible = "arm,pl022", "arm,primecell"; 184 reg = <0x8b1a000 0x1000>; 185 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 186 num-cs = <1>; 187 cs-gpios = <&gpio7 1 0>; 188 clocks = <&crg HISTB_SPI0_CLK>; 189 clock-names = "apb_pclk"; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 status = "disabled"; 193 }; 194 195 emmc: mmc@9830000 { 196 compatible = "snps,dw-mshc"; 197 reg = <0x9830000 0x10000>; 198 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&crg HISTB_MMC_CIU_CLK>, 200 <&crg HISTB_MMC_BIU_CLK>; 201 clock-names = "ciu", "biu"; 202 }; 203 204 gpio0: gpio@8b20000 { 205 compatible = "arm,pl061", "arm,primecell"; 206 reg = <0x8b20000 0x1000>; 207 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 208 gpio-controller; 209 #gpio-cells = <2>; 210 interrupt-controller; 211 #interrupt-cells = <2>; 212 clocks = <&crg HISTB_APB_CLK>; 213 clock-names = "apb_pclk"; 214 status = "disabled"; 215 }; 216 217 gpio1: gpio@8b21000 { 218 compatible = "arm,pl061", "arm,primecell"; 219 reg = <0x8b21000 0x1000>; 220 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 221 gpio-controller; 222 #gpio-cells = <2>; 223 interrupt-controller; 224 #interrupt-cells = <2>; 225 clocks = <&crg HISTB_APB_CLK>; 226 clock-names = "apb_pclk"; 227 status = "disabled"; 228 }; 229 230 gpio2: gpio@8b22000 { 231 compatible = "arm,pl061", "arm,primecell"; 232 reg = <0x8b22000 0x1000>; 233 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 234 gpio-controller; 235 #gpio-cells = <2>; 236 interrupt-controller; 237 #interrupt-cells = <2>; 238 clocks = <&crg HISTB_APB_CLK>; 239 clock-names = "apb_pclk"; 240 status = "disabled"; 241 }; 242 243 gpio3: gpio@8b23000 { 244 compatible = "arm,pl061", "arm,primecell"; 245 reg = <0x8b23000 0x1000>; 246 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 247 gpio-controller; 248 #gpio-cells = <2>; 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 clocks = <&crg HISTB_APB_CLK>; 252 clock-names = "apb_pclk"; 253 status = "disabled"; 254 }; 255 256 gpio4: gpio@8b24000 { 257 compatible = "arm,pl061", "arm,primecell"; 258 reg = <0x8b24000 0x1000>; 259 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 260 gpio-controller; 261 #gpio-cells = <2>; 262 interrupt-controller; 263 #interrupt-cells = <2>; 264 clocks = <&crg HISTB_APB_CLK>; 265 clock-names = "apb_pclk"; 266 status = "disabled"; 267 }; 268 269 gpio5: gpio@8004000 { 270 compatible = "arm,pl061", "arm,primecell"; 271 reg = <0x8004000 0x1000>; 272 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 273 gpio-controller; 274 #gpio-cells = <2>; 275 interrupt-controller; 276 #interrupt-cells = <2>; 277 clocks = <&crg HISTB_APB_CLK>; 278 clock-names = "apb_pclk"; 279 status = "disabled"; 280 }; 281 282 gpio6: gpio@8b26000 { 283 compatible = "arm,pl061", "arm,primecell"; 284 reg = <0x8b26000 0x1000>; 285 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 286 gpio-controller; 287 #gpio-cells = <2>; 288 interrupt-controller; 289 #interrupt-cells = <2>; 290 clocks = <&crg HISTB_APB_CLK>; 291 clock-names = "apb_pclk"; 292 status = "disabled"; 293 }; 294 295 gpio7: gpio@8b27000 { 296 compatible = "arm,pl061", "arm,primecell"; 297 reg = <0x8b27000 0x1000>; 298 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 299 gpio-controller; 300 #gpio-cells = <2>; 301 interrupt-controller; 302 #interrupt-cells = <2>; 303 clocks = <&crg HISTB_APB_CLK>; 304 clock-names = "apb_pclk"; 305 status = "disabled"; 306 }; 307 308 gpio8: gpio@8b28000 { 309 compatible = "arm,pl061", "arm,primecell"; 310 reg = <0x8b28000 0x1000>; 311 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 312 gpio-controller; 313 #gpio-cells = <2>; 314 interrupt-controller; 315 #interrupt-cells = <2>; 316 clocks = <&crg HISTB_APB_CLK>; 317 clock-names = "apb_pclk"; 318 status = "disabled"; 319 }; 320 321 gpio9: gpio@8b29000 { 322 compatible = "arm,pl061", "arm,primecell"; 323 reg = <0x8b29000 0x1000>; 324 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 325 gpio-controller; 326 #gpio-cells = <2>; 327 interrupt-controller; 328 #interrupt-cells = <2>; 329 clocks = <&crg HISTB_APB_CLK>; 330 clock-names = "apb_pclk"; 331 status = "disabled"; 332 }; 333 334 gpio10: gpio@8b2a000 { 335 compatible = "arm,pl061", "arm,primecell"; 336 reg = <0x8b2a000 0x1000>; 337 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 338 gpio-controller; 339 #gpio-cells = <2>; 340 interrupt-controller; 341 #interrupt-cells = <2>; 342 clocks = <&crg HISTB_APB_CLK>; 343 clock-names = "apb_pclk"; 344 status = "disabled"; 345 }; 346 347 gpio11: gpio@8b2b000 { 348 compatible = "arm,pl061", "arm,primecell"; 349 reg = <0x8b2b000 0x1000>; 350 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 351 gpio-controller; 352 #gpio-cells = <2>; 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 clocks = <&crg HISTB_APB_CLK>; 356 clock-names = "apb_pclk"; 357 status = "disabled"; 358 }; 359 360 gpio12: gpio@8b2c000 { 361 compatible = "arm,pl061", "arm,primecell"; 362 reg = <0x8b2c000 0x1000>; 363 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 364 gpio-controller; 365 #gpio-cells = <2>; 366 interrupt-controller; 367 #interrupt-cells = <2>; 368 clocks = <&crg HISTB_APB_CLK>; 369 clock-names = "apb_pclk"; 370 status = "disabled"; 371 }; 372 373 gmac0: ethernet@9840000 { 374 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; 375 reg = <0x9840000 0x1000>, 376 <0x984300c 0x4>; 377 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&crg HISTB_ETH0_MAC_CLK>, 379 <&crg HISTB_ETH0_MACIF_CLK>; 380 clock-names = "mac_core", "mac_ifc"; 381 resets = <&crg 0xcc 8>, 382 <&crg 0xcc 10>, 383 <&gmacphyrst 0>; 384 reset-names = "mac_core", "mac_ifc", "phy"; 385 status = "disabled"; 386 }; 387 388 gmac1: ethernet@9841000 { 389 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; 390 reg = <0x9841000 0x1000>, 391 <0x9843010 0x4>; 392 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&crg HISTB_ETH1_MAC_CLK>, 394 <&crg HISTB_ETH1_MACIF_CLK>; 395 clock-names = "mac_core", "mac_ifc"; 396 resets = <&crg 0xcc 9>, 397 <&crg 0xcc 11>, 398 <&gmacphyrst 1>; 399 reset-names = "mac_core", "mac_ifc", "phy"; 400 status = "disabled"; 401 }; 402 403 ir: ir@8001000 { 404 compatible = "hisilicon,hix5hd2-ir"; 405 reg = <0x8001000 0x1000>; 406 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&sysctrl HISTB_IR_CLK>; 408 status = "disabled"; 409 }; 410 }; 411}; 412