1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * NXP lx2160a SOC common device tree source 4 * 5 * Copyright 2018 NXP 6 * 7 */ 8 9/ { 10 compatible = "fsl,lx2160a"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 memory@80000000 { 16 device_type = "memory"; 17 reg = <0x00000000 0x80000000 0 0x80000000>; 18 /* DRAM space - 1, size : 2 GB DRAM */ 19 }; 20 21 sysclk: sysclk { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <100000000>; 25 clock-output-names = "sysclk"; 26 }; 27 28 clockgen: clocking@1300000 { 29 compatible = "fsl,ls2080a-clockgen"; 30 reg = <0 0x1300000 0 0xa0000>; 31 #clock-cells = <2>; 32 clocks = <&sysclk>; 33 }; 34 35 gic: interrupt-controller@6000000 { 36 compatible = "arm,gic-v3"; 37 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 38 <0x0 0x06200000 0 0x100000>; /* GICR */ 39 #interrupt-cells = <3>; 40 interrupt-controller; 41 interrupts = <1 9 0x4>; 42 }; 43 44 timer { 45 compatible = "arm,armv8-timer"; 46 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ 47 <1 14 0x8>, /* Physical NS PPI, active-low */ 48 <1 11 0x8>, /* Virtual PPI, active-low */ 49 <1 10 0x8>; /* Hypervisor PPI, active-low */ 50 }; 51 52 uart0: serial@21c0000 { 53 compatible = "arm,pl011"; 54 reg = <0x0 0x21c0000 0x0 0x1000>; 55 clocks = <&clockgen 4 0>; 56 }; 57 58 uart1: serial@21d0000 { 59 compatible = "arm,pl011"; 60 reg = <0x0 0x21d0000 0x0 0x1000>; 61 clocks = <&clockgen 4 0>; 62 }; 63 64 uart2: serial@21e0000 { 65 compatible = "arm,pl011"; 66 reg = <0x0 0x21e0000 0x0 0x1000>; 67 clocks = <&clockgen 4 0>; 68 status = "disabled"; 69 }; 70 71 uart3: serial@21f0000 { 72 compatible = "arm,pl011"; 73 reg = <0x0 0x21f0000 0x0 0x1000>; 74 clocks = <&clockgen 4 0>; 75 status = "disabled"; 76 }; 77 78 dspi0: dspi@2100000 { 79 compatible = "fsl,vf610-dspi"; 80 #address-cells = <1>; 81 #size-cells = <0>; 82 reg = <0x0 0x2100000 0x0 0x10000>; 83 interrupts = <0 26 0x4>; /* Level high type */ 84 num-cs = <6>; 85 }; 86 87 dspi1: dspi@2110000 { 88 compatible = "fsl,vf610-dspi"; 89 #address-cells = <1>; 90 #size-cells = <0>; 91 reg = <0x0 0x2110000 0x0 0x10000>; 92 interrupts = <0 240 0x4>; /* Level high type */ 93 num-cs = <6>; 94 }; 95 96 dspi2: dspi@2120000 { 97 compatible = "fsl,vf610-dspi"; 98 #address-cells = <1>; 99 #size-cells = <0>; 100 reg = <0x0 0x2120000 0x0 0x10000>; 101 interrupts = <0 241 0x4>; /* Level high type */ 102 num-cs = <6>; 103 }; 104 105 usb0: usb3@3100000 { 106 compatible = "fsl,layerscape-dwc3"; 107 reg = <0x0 0x3100000 0x0 0x10000>; 108 interrupts = <0 80 0x4>; /* Level high type */ 109 dr_mode = "host"; 110 }; 111 112 usb1: usb3@3110000 { 113 compatible = "fsl,layerscape-dwc3"; 114 reg = <0x0 0x3110000 0x0 0x10000>; 115 interrupts = <0 81 0x4>; /* Level high type */ 116 dr_mode = "host"; 117 }; 118}; 119