1*4909b89eSPriyanka Jain// SPDX-License-Identifier: GPL-2.0+ OR X11 2*4909b89eSPriyanka Jain/* 3*4909b89eSPriyanka Jain * NXP lx2160a SOC common device tree source 4*4909b89eSPriyanka Jain * 5*4909b89eSPriyanka Jain * Copyright 2018 NXP 6*4909b89eSPriyanka Jain * 7*4909b89eSPriyanka Jain */ 8*4909b89eSPriyanka Jain 9*4909b89eSPriyanka Jain/ { 10*4909b89eSPriyanka Jain compatible = "fsl,lx2160a"; 11*4909b89eSPriyanka Jain interrupt-parent = <&gic>; 12*4909b89eSPriyanka Jain #address-cells = <2>; 13*4909b89eSPriyanka Jain #size-cells = <2>; 14*4909b89eSPriyanka Jain 15*4909b89eSPriyanka Jain memory@80000000 { 16*4909b89eSPriyanka Jain device_type = "memory"; 17*4909b89eSPriyanka Jain reg = <0x00000000 0x80000000 0 0x80000000>; 18*4909b89eSPriyanka Jain /* DRAM space - 1, size : 2 GB DRAM */ 19*4909b89eSPriyanka Jain }; 20*4909b89eSPriyanka Jain 21*4909b89eSPriyanka Jain sysclk: sysclk { 22*4909b89eSPriyanka Jain compatible = "fixed-clock"; 23*4909b89eSPriyanka Jain #clock-cells = <0>; 24*4909b89eSPriyanka Jain clock-frequency = <100000000>; 25*4909b89eSPriyanka Jain clock-output-names = "sysclk"; 26*4909b89eSPriyanka Jain }; 27*4909b89eSPriyanka Jain 28*4909b89eSPriyanka Jain clockgen: clocking@1300000 { 29*4909b89eSPriyanka Jain compatible = "fsl,ls2080a-clockgen"; 30*4909b89eSPriyanka Jain reg = <0 0x1300000 0 0xa0000>; 31*4909b89eSPriyanka Jain #clock-cells = <2>; 32*4909b89eSPriyanka Jain clocks = <&sysclk>; 33*4909b89eSPriyanka Jain }; 34*4909b89eSPriyanka Jain 35*4909b89eSPriyanka Jain gic: interrupt-controller@6000000 { 36*4909b89eSPriyanka Jain compatible = "arm,gic-v3"; 37*4909b89eSPriyanka Jain reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 38*4909b89eSPriyanka Jain <0x0 0x06200000 0 0x100000>; /* GICR */ 39*4909b89eSPriyanka Jain #interrupt-cells = <3>; 40*4909b89eSPriyanka Jain interrupt-controller; 41*4909b89eSPriyanka Jain interrupts = <1 9 0x4>; 42*4909b89eSPriyanka Jain }; 43*4909b89eSPriyanka Jain 44*4909b89eSPriyanka Jain timer { 45*4909b89eSPriyanka Jain compatible = "arm,armv8-timer"; 46*4909b89eSPriyanka Jain interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ 47*4909b89eSPriyanka Jain <1 14 0x8>, /* Physical NS PPI, active-low */ 48*4909b89eSPriyanka Jain <1 11 0x8>, /* Virtual PPI, active-low */ 49*4909b89eSPriyanka Jain <1 10 0x8>; /* Hypervisor PPI, active-low */ 50*4909b89eSPriyanka Jain }; 51*4909b89eSPriyanka Jain 52*4909b89eSPriyanka Jain uart0: serial@21c0000 { 53*4909b89eSPriyanka Jain compatible = "arm,pl011"; 54*4909b89eSPriyanka Jain reg = <0x0 0x21c0000 0x0 0x1000>; 55*4909b89eSPriyanka Jain clocks = <&clockgen 4 0>; 56*4909b89eSPriyanka Jain }; 57*4909b89eSPriyanka Jain 58*4909b89eSPriyanka Jain uart1: serial@21d0000 { 59*4909b89eSPriyanka Jain compatible = "arm,pl011"; 60*4909b89eSPriyanka Jain reg = <0x0 0x21d0000 0x0 0x1000>; 61*4909b89eSPriyanka Jain clocks = <&clockgen 4 0>; 62*4909b89eSPriyanka Jain }; 63*4909b89eSPriyanka Jain 64*4909b89eSPriyanka Jain uart2: serial@21e0000 { 65*4909b89eSPriyanka Jain compatible = "arm,pl011"; 66*4909b89eSPriyanka Jain reg = <0x0 0x21e0000 0x0 0x1000>; 67*4909b89eSPriyanka Jain clocks = <&clockgen 4 0>; 68*4909b89eSPriyanka Jain status = "disabled"; 69*4909b89eSPriyanka Jain }; 70*4909b89eSPriyanka Jain 71*4909b89eSPriyanka Jain uart3: serial@21f0000 { 72*4909b89eSPriyanka Jain compatible = "arm,pl011"; 73*4909b89eSPriyanka Jain reg = <0x0 0x21f0000 0x0 0x1000>; 74*4909b89eSPriyanka Jain clocks = <&clockgen 4 0>; 75*4909b89eSPriyanka Jain status = "disabled"; 76*4909b89eSPriyanka Jain }; 77*4909b89eSPriyanka Jain 78*4909b89eSPriyanka Jain dspi0: dspi@2100000 { 79*4909b89eSPriyanka Jain compatible = "fsl,vf610-dspi"; 80*4909b89eSPriyanka Jain #address-cells = <1>; 81*4909b89eSPriyanka Jain #size-cells = <0>; 82*4909b89eSPriyanka Jain reg = <0x0 0x2100000 0x0 0x10000>; 83*4909b89eSPriyanka Jain interrupts = <0 26 0x4>; /* Level high type */ 84*4909b89eSPriyanka Jain num-cs = <6>; 85*4909b89eSPriyanka Jain }; 86*4909b89eSPriyanka Jain 87*4909b89eSPriyanka Jain dspi1: dspi@2110000 { 88*4909b89eSPriyanka Jain compatible = "fsl,vf610-dspi"; 89*4909b89eSPriyanka Jain #address-cells = <1>; 90*4909b89eSPriyanka Jain #size-cells = <0>; 91*4909b89eSPriyanka Jain reg = <0x0 0x2110000 0x0 0x10000>; 92*4909b89eSPriyanka Jain interrupts = <0 240 0x4>; /* Level high type */ 93*4909b89eSPriyanka Jain num-cs = <6>; 94*4909b89eSPriyanka Jain }; 95*4909b89eSPriyanka Jain 96*4909b89eSPriyanka Jain dspi2: dspi@2120000 { 97*4909b89eSPriyanka Jain compatible = "fsl,vf610-dspi"; 98*4909b89eSPriyanka Jain #address-cells = <1>; 99*4909b89eSPriyanka Jain #size-cells = <0>; 100*4909b89eSPriyanka Jain reg = <0x0 0x2120000 0x0 0x10000>; 101*4909b89eSPriyanka Jain interrupts = <0 241 0x4>; /* Level high type */ 102*4909b89eSPriyanka Jain num-cs = <6>; 103*4909b89eSPriyanka Jain }; 104*4909b89eSPriyanka Jain 105*4909b89eSPriyanka Jain usb0: usb3@3100000 { 106*4909b89eSPriyanka Jain compatible = "fsl,layerscape-dwc3"; 107*4909b89eSPriyanka Jain reg = <0x0 0x3100000 0x0 0x10000>; 108*4909b89eSPriyanka Jain interrupts = <0 80 0x4>; /* Level high type */ 109*4909b89eSPriyanka Jain dr_mode = "host"; 110*4909b89eSPriyanka Jain }; 111*4909b89eSPriyanka Jain 112*4909b89eSPriyanka Jain usb1: usb3@3110000 { 113*4909b89eSPriyanka Jain compatible = "fsl,layerscape-dwc3"; 114*4909b89eSPriyanka Jain reg = <0x0 0x3110000 0x0 0x10000>; 115*4909b89eSPriyanka Jain interrupts = <0 81 0x4>; /* Level high type */ 116*4909b89eSPriyanka Jain dr_mode = "host"; 117*4909b89eSPriyanka Jain }; 118*4909b89eSPriyanka Jain}; 119