1/* 2 * Device Tree Include file for Freescale Layerscape-1043A family SoC. 3 * 4 * Copyright (C) 2014-2015, Freescale Semiconductor 5 * 6 * Mingkai Hu <Mingkai.hu@freescale.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13/include/ "skeleton64.dtsi" 14 15/ { 16 compatible = "fsl,ls1043a"; 17 interrupt-parent = <&gic>; 18 19 sysclk: sysclk { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <100000000>; 23 clock-output-names = "sysclk"; 24 }; 25 26 gic: interrupt-controller@1400000 { 27 compatible = "arm,gic-400"; 28 #interrupt-cells = <3>; 29 interrupt-controller; 30 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 31 <0x0 0x1402000 0 0x2000>, /* GICC */ 32 <0x0 0x1404000 0 0x2000>, /* GICH */ 33 <0x0 0x1406000 0 0x2000>; /* GICV */ 34 interrupts = <1 9 0xf08>; 35 }; 36 37 soc { 38 compatible = "simple-bus"; 39 #address-cells = <2>; 40 #size-cells = <2>; 41 ranges; 42 43 clockgen: clocking@1ee1000 { 44 compatible = "fsl,ls1043a-clockgen"; 45 reg = <0x0 0x1ee1000 0x0 0x1000>; 46 #clock-cells = <2>; 47 clocks = <&sysclk>; 48 }; 49 50 dspi0: dspi@2100000 { 51 compatible = "fsl,vf610-dspi"; 52 #address-cells = <1>; 53 #size-cells = <0>; 54 reg = <0x0 0x2100000 0x0 0x10000>; 55 interrupts = <0 64 0x4>; 56 clock-names = "dspi"; 57 clocks = <&clockgen 4 0>; 58 num-cs = <6>; 59 big-endian; 60 status = "disabled"; 61 }; 62 63 dspi1: dspi@2110000 { 64 compatible = "fsl,vf610-dspi"; 65 #address-cells = <1>; 66 #size-cells = <0>; 67 reg = <0x0 0x2110000 0x0 0x10000>; 68 interrupts = <0 65 0x4>; 69 clock-names = "dspi"; 70 clocks = <&clockgen 4 0>; 71 num-cs = <6>; 72 big-endian; 73 status = "disabled"; 74 }; 75 76 ifc: ifc@1530000 { 77 compatible = "fsl,ifc", "simple-bus"; 78 reg = <0x0 0x1530000 0x0 0x10000>; 79 interrupts = <0 43 0x4>; 80 }; 81 82 i2c0: i2c@2180000 { 83 compatible = "fsl,vf610-i2c"; 84 #address-cells = <1>; 85 #size-cells = <0>; 86 reg = <0x0 0x2180000 0x0 0x10000>; 87 interrupts = <0 56 0x4>; 88 clock-names = "i2c"; 89 clocks = <&clockgen 4 0>; 90 status = "disabled"; 91 }; 92 93 i2c1: i2c@2190000 { 94 compatible = "fsl,vf610-i2c"; 95 #address-cells = <1>; 96 #size-cells = <0>; 97 reg = <0x0 0x2190000 0x0 0x10000>; 98 interrupts = <0 57 0x4>; 99 clock-names = "i2c"; 100 clocks = <&clockgen 4 0>; 101 status = "disabled"; 102 }; 103 104 i2c2: i2c@21a0000 { 105 compatible = "fsl,vf610-i2c"; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 reg = <0x0 0x21a0000 0x0 0x10000>; 109 interrupts = <0 58 0x4>; 110 clock-names = "i2c"; 111 clocks = <&clockgen 4 0>; 112 status = "disabled"; 113 }; 114 115 i2c3: i2c@21b0000 { 116 compatible = "fsl,vf610-i2c"; 117 #address-cells = <1>; 118 #size-cells = <0>; 119 reg = <0x0 0x21b0000 0x0 0x10000>; 120 interrupts = <0 59 0x4>; 121 clock-names = "i2c"; 122 clocks = <&clockgen 4 0>; 123 status = "disabled"; 124 }; 125 126 duart0: serial@21c0500 { 127 compatible = "fsl,ns16550", "ns16550a"; 128 reg = <0x00 0x21c0500 0x0 0x100>; 129 interrupts = <0 54 0x4>; 130 clocks = <&clockgen 4 0>; 131 }; 132 133 duart1: serial@21c0600 { 134 compatible = "fsl,ns16550", "ns16550a"; 135 reg = <0x00 0x21c0600 0x0 0x100>; 136 interrupts = <0 54 0x4>; 137 clocks = <&clockgen 4 0>; 138 }; 139 140 duart2: serial@21d0500 { 141 compatible = "fsl,ns16550", "ns16550a"; 142 reg = <0x0 0x21d0500 0x0 0x100>; 143 interrupts = <0 55 0x4>; 144 clocks = <&clockgen 4 0>; 145 }; 146 147 duart3: serial@21d0600 { 148 compatible = "fsl,ns16550", "ns16550a"; 149 reg = <0x0 0x21d0600 0x0 0x100>; 150 interrupts = <0 55 0x4>; 151 clocks = <&clockgen 4 0>; 152 }; 153 154 lpuart0: serial@2950000 { 155 compatible = "fsl,ls1021a-lpuart"; 156 reg = <0x0 0x2950000 0x0 0x1000>; 157 interrupts = <0 48 0x4>; 158 clocks = <&sysclk>; 159 clock-names = "ipg"; 160 status = "disabled"; 161 }; 162 163 lpuart1: serial@2960000 { 164 compatible = "fsl,ls1021a-lpuart"; 165 reg = <0x0 0x2960000 0x0 0x1000>; 166 interrupts = <0 49 0x4>; 167 clocks = <&sysclk>; 168 clock-names = "ipg"; 169 status = "disabled"; 170 }; 171 172 lpuart2: serial@2970000 { 173 compatible = "fsl,ls1021a-lpuart"; 174 reg = <0x0 0x2970000 0x0 0x1000>; 175 interrupts = <0 50 0x4>; 176 clock-names = "ipg"; 177 clocks = <&sysclk>; 178 status = "disabled"; 179 }; 180 181 lpuart3: serial@2980000 { 182 compatible = "fsl,ls1021a-lpuart"; 183 reg = <0x0 0x2980000 0x0 0x1000>; 184 interrupts = <0 51 0x4>; 185 clocks = <&sysclk>; 186 clock-names = "ipg"; 187 status = "disabled"; 188 }; 189 190 lpuart4: serial@2990000 { 191 compatible = "fsl,ls1021a-lpuart"; 192 reg = <0x0 0x2990000 0x0 0x1000>; 193 interrupts = <0 52 0x4>; 194 clocks = <&sysclk>; 195 clock-names = "ipg"; 196 status = "disabled"; 197 }; 198 199 lpuart5: serial@29a0000 { 200 compatible = "fsl,ls1021a-lpuart"; 201 reg = <0x0 0x29a0000 0x0 0x1000>; 202 interrupts = <0 53 0x4>; 203 clocks = <&sysclk>; 204 clock-names = "ipg"; 205 status = "disabled"; 206 }; 207 qspi: quadspi@1550000 { 208 compatible = "fsl,vf610-qspi"; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 reg = <0x0 0x1550000 0x0 0x10000>, 212 <0x0 0x40000000 0x0 0x4000000>; 213 reg-names = "QuadSPI", "QuadSPI-memory"; 214 num-cs = <2>; 215 big-endian; 216 status = "disabled"; 217 }; 218 219 usb0: usb3@2f00000 { 220 compatible = "fsl,layerscape-dwc3"; 221 reg = <0x0 0x2f00000 0x0 0x10000>; 222 interrupts = <0 60 0x4>; 223 dr_mode = "host"; 224 }; 225 226 usb1: usb3@3000000 { 227 compatible = "fsl,layerscape-dwc3"; 228 reg = <0x0 0x3000000 0x0 0x10000>; 229 interrupts = <0 61 0x4>; 230 dr_mode = "host"; 231 }; 232 233 usb2: usb3@3100000 { 234 compatible = "fsl,layerscape-dwc3"; 235 reg = <0x0 0x3100000 0x0 0x10000>; 236 interrupts = <0 63 0x4>; 237 dr_mode = "host"; 238 }; 239 240 pcie@3400000 { 241 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 242 reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */ 243 0x00 0x03410000 0x0 0x10000 /* lut registers */ 244 0x40 0x00000000 0x0 0x20000>; /* configuration space */ 245 reg-names = "dbi", "lut", "config"; 246 big-endian; 247 #address-cells = <3>; 248 #size-cells = <2>; 249 device_type = "pci"; 250 bus-range = <0x0 0xff>; 251 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */ 252 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 253 }; 254 255 pcie@3500000 { 256 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 257 reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */ 258 0x00 0x03510000 0x0 0x10000 /* lut registers */ 259 0x48 0x00000000 0x0 0x20000>; /* configuration space */ 260 reg-names = "dbi", "lut", "config"; 261 big-endian; 262 #address-cells = <3>; 263 #size-cells = <2>; 264 device_type = "pci"; 265 num-lanes = <2>; 266 bus-range = <0x0 0xff>; 267 ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */ 268 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 269 }; 270 271 pcie@3600000 { 272 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 273 reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */ 274 0x00 0x03610000 0x0 0x10000 /* lut registers */ 275 0x50 0x00000000 0x0 0x20000>; /* configuration space */ 276 reg-names = "dbi", "lut", "config"; 277 big-endian; 278 #address-cells = <3>; 279 #size-cells = <2>; 280 device_type = "pci"; 281 bus-range = <0x0 0xff>; 282 ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */ 283 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 284 }; 285 }; 286}; 287