1/* 2 * Device Tree Include file for Freescale Layerscape-1043A family SoC. 3 * 4 * Copyright (C) 2014-2015, Freescale Semiconductor 5 * 6 * Mingkai Hu <Mingkai.hu@freescale.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13/include/ "skeleton64.dtsi" 14 15/ { 16 compatible = "fsl,ls1043a"; 17 interrupt-parent = <&gic>; 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a53"; 25 reg = <0x0 0x0>; 26 clocks = <&clockgen 1 0>; 27 }; 28 29 cpu1: cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a53"; 32 reg = <0x0 0x1>; 33 clocks = <&clockgen 1 0>; 34 }; 35 36 cpu2: cpu@2 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53"; 39 reg = <0x0 0x2>; 40 clocks = <&clockgen 1 0>; 41 }; 42 43 cpu3: cpu@3 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 reg = <0x0 0x3>; 47 clocks = <&clockgen 1 0>; 48 }; 49 }; 50 51 sysclk: sysclk { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <100000000>; 55 clock-output-names = "sysclk"; 56 }; 57 58 gic: interrupt-controller@1400000 { 59 compatible = "arm,gic-400"; 60 #interrupt-cells = <3>; 61 interrupt-controller; 62 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 63 <0x0 0x1402000 0 0x2000>, /* GICC */ 64 <0x0 0x1404000 0 0x2000>, /* GICH */ 65 <0x0 0x1406000 0 0x2000>; /* GICV */ 66 interrupts = <1 9 0xf08>; 67 }; 68 69 soc { 70 compatible = "simple-bus"; 71 #address-cells = <2>; 72 #size-cells = <2>; 73 ranges; 74 75 clockgen: clocking@1ee1000 { 76 compatible = "fsl,ls1043a-clockgen"; 77 reg = <0x0 0x1ee1000 0x0 0x1000>; 78 #clock-cells = <2>; 79 clocks = <&sysclk>; 80 }; 81 82 dspi0: dspi@2100000 { 83 compatible = "fsl,vf610-dspi"; 84 #address-cells = <1>; 85 #size-cells = <0>; 86 reg = <0x0 0x2100000 0x0 0x10000>; 87 interrupts = <0 64 0x4>; 88 clock-names = "dspi"; 89 clocks = <&clockgen 4 0>; 90 num-cs = <6>; 91 big-endian; 92 status = "disabled"; 93 }; 94 95 dspi1: dspi@2110000 { 96 compatible = "fsl,vf610-dspi"; 97 #address-cells = <1>; 98 #size-cells = <0>; 99 reg = <0x0 0x2110000 0x0 0x10000>; 100 interrupts = <0 65 0x4>; 101 clock-names = "dspi"; 102 clocks = <&clockgen 4 0>; 103 num-cs = <6>; 104 big-endian; 105 status = "disabled"; 106 }; 107 108 ifc: ifc@1530000 { 109 compatible = "fsl,ifc", "simple-bus"; 110 reg = <0x0 0x1530000 0x0 0x10000>; 111 interrupts = <0 43 0x4>; 112 }; 113 114 i2c0: i2c@2180000 { 115 compatible = "fsl,vf610-i2c"; 116 #address-cells = <1>; 117 #size-cells = <0>; 118 reg = <0x0 0x2180000 0x0 0x10000>; 119 interrupts = <0 56 0x4>; 120 clock-names = "i2c"; 121 clocks = <&clockgen 4 0>; 122 status = "disabled"; 123 }; 124 125 i2c1: i2c@2190000 { 126 compatible = "fsl,vf610-i2c"; 127 #address-cells = <1>; 128 #size-cells = <0>; 129 reg = <0x0 0x2190000 0x0 0x10000>; 130 interrupts = <0 57 0x4>; 131 clock-names = "i2c"; 132 clocks = <&clockgen 4 0>; 133 status = "disabled"; 134 }; 135 136 i2c2: i2c@21a0000 { 137 compatible = "fsl,vf610-i2c"; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 reg = <0x0 0x21a0000 0x0 0x10000>; 141 interrupts = <0 58 0x4>; 142 clock-names = "i2c"; 143 clocks = <&clockgen 4 0>; 144 status = "disabled"; 145 }; 146 147 i2c3: i2c@21b0000 { 148 compatible = "fsl,vf610-i2c"; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 reg = <0x0 0x21b0000 0x0 0x10000>; 152 interrupts = <0 59 0x4>; 153 clock-names = "i2c"; 154 clocks = <&clockgen 4 0>; 155 status = "disabled"; 156 }; 157 158 duart0: serial@21c0500 { 159 compatible = "fsl,ns16550", "ns16550a"; 160 reg = <0x00 0x21c0500 0x0 0x100>; 161 interrupts = <0 54 0x4>; 162 clocks = <&clockgen 4 0>; 163 }; 164 165 duart1: serial@21c0600 { 166 compatible = "fsl,ns16550", "ns16550a"; 167 reg = <0x00 0x21c0600 0x0 0x100>; 168 interrupts = <0 54 0x4>; 169 clocks = <&clockgen 4 0>; 170 }; 171 172 duart2: serial@21d0500 { 173 compatible = "fsl,ns16550", "ns16550a"; 174 reg = <0x0 0x21d0500 0x0 0x100>; 175 interrupts = <0 55 0x4>; 176 clocks = <&clockgen 4 0>; 177 }; 178 179 duart3: serial@21d0600 { 180 compatible = "fsl,ns16550", "ns16550a"; 181 reg = <0x0 0x21d0600 0x0 0x100>; 182 interrupts = <0 55 0x4>; 183 clocks = <&clockgen 4 0>; 184 }; 185 186 lpuart0: serial@2950000 { 187 compatible = "fsl,ls1021a-lpuart"; 188 reg = <0x0 0x2950000 0x0 0x1000>; 189 interrupts = <0 48 0x4>; 190 clocks = <&sysclk>; 191 clock-names = "ipg"; 192 status = "disabled"; 193 }; 194 195 lpuart1: serial@2960000 { 196 compatible = "fsl,ls1021a-lpuart"; 197 reg = <0x0 0x2960000 0x0 0x1000>; 198 interrupts = <0 49 0x4>; 199 clocks = <&sysclk>; 200 clock-names = "ipg"; 201 status = "disabled"; 202 }; 203 204 lpuart2: serial@2970000 { 205 compatible = "fsl,ls1021a-lpuart"; 206 reg = <0x0 0x2970000 0x0 0x1000>; 207 interrupts = <0 50 0x4>; 208 clock-names = "ipg"; 209 clocks = <&sysclk>; 210 status = "disabled"; 211 }; 212 213 lpuart3: serial@2980000 { 214 compatible = "fsl,ls1021a-lpuart"; 215 reg = <0x0 0x2980000 0x0 0x1000>; 216 interrupts = <0 51 0x4>; 217 clocks = <&sysclk>; 218 clock-names = "ipg"; 219 status = "disabled"; 220 }; 221 222 lpuart4: serial@2990000 { 223 compatible = "fsl,ls1021a-lpuart"; 224 reg = <0x0 0x2990000 0x0 0x1000>; 225 interrupts = <0 52 0x4>; 226 clocks = <&sysclk>; 227 clock-names = "ipg"; 228 status = "disabled"; 229 }; 230 231 lpuart5: serial@29a0000 { 232 compatible = "fsl,ls1021a-lpuart"; 233 reg = <0x0 0x29a0000 0x0 0x1000>; 234 interrupts = <0 53 0x4>; 235 clocks = <&sysclk>; 236 clock-names = "ipg"; 237 status = "disabled"; 238 }; 239 qspi: quadspi@1550000 { 240 compatible = "fsl,vf610-qspi"; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 reg = <0x0 0x1550000 0x0 0x10000>, 244 <0x0 0x40000000 0x0 0x4000000>; 245 reg-names = "QuadSPI", "QuadSPI-memory"; 246 num-cs = <2>; 247 big-endian; 248 status = "disabled"; 249 }; 250 }; 251}; 252