1/*
2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
3 *
4 * Copyright (C) 2015, Freescale Semiconductor
5 *
6 * Mingkai Hu <Mingkai.hu@freescale.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2.  This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13/include/ "fsl-ls1043a.dtsi"
14
15/ {
16	model = "LS1043A QDS Board";
17};
18
19&i2c0 {
20	status = "okay";
21	pca9547@77 {
22		compatible = "philips,pca9547";
23		reg = <0x77>;
24		#address-cells = <1>;
25		#size-cells = <0>;
26
27		i2c@0 {
28			#address-cells = <1>;
29			#size-cells = <0>;
30			reg = <0x0>;
31
32			rtc@68 {
33				compatible = "dallas,ds3232";
34				reg = <0x68>;
35				/* IRQ10_B */
36				interrupts = <0 150 0x4>;
37			};
38		};
39
40		i2c@2 {
41			#address-cells = <1>;
42			#size-cells = <0>;
43			reg = <0x2>;
44
45			ina220@40 {
46				compatible = "ti,ina220";
47				reg = <0x40>;
48				shunt-resistor = <1000>;
49			};
50
51			ina220@41 {
52				compatible = "ti,ina220";
53				reg = <0x41>;
54				shunt-resistor = <1000>;
55			};
56		};
57
58		i2c@3 {
59			#address-cells = <1>;
60			#size-cells = <0>;
61			reg = <0x3>;
62
63			eeprom@56 {
64				compatible = "at24,24c512";
65				reg = <0x56>;
66			};
67
68			eeprom@57 {
69				compatible = "at24,24c512";
70				reg = <0x57>;
71			};
72
73			adt7461a@4c {
74				compatible = "adt7461a";
75				reg = <0x4c>;
76			};
77		};
78	};
79};
80
81&ifc {
82	#address-cells = <2>;
83	#size-cells = <1>;
84	/* NOR, NAND Flashes and FPGA on board */
85	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
86		  0x2 0x0 0x0 0x7e800000 0x00010000
87		  0x3 0x0 0x0 0x7fb00000 0x00000100>;
88	status = "okay";
89
90	nor@0,0 {
91		#address-cells = <1>;
92		#size-cells = <1>;
93		compatible = "cfi-flash";
94		reg = <0x0 0x0 0x8000000>;
95		bank-width = <2>;
96		device-width = <1>;
97	};
98
99	nand@2,0 {
100		compatible = "fsl,ifc-nand";
101		#address-cells = <1>;
102		#size-cells = <1>;
103		reg = <0x1 0x0 0x10000>;
104	};
105
106	fpga: board-control@3,0 {
107		#address-cells = <1>;
108		#size-cells = <1>;
109		compatible = "simple-bus";
110		reg = <0x3 0x0 0x0000100>;
111		bank-width = <1>;
112		device-width = <1>;
113		ranges = <0 3 0 0x100>;
114	};
115};
116
117&duart0 {
118	status = "okay";
119};
120
121&duart1 {
122	status = "okay";
123};
124
125&lpuart0 {
126	status = "okay";
127};
128