1*8e728aa9SWenbin Song/*
2*8e728aa9SWenbin Song * Device Tree Include file for Freescale Layerscape-1043A family SoC.
3*8e728aa9SWenbin Song *
4*8e728aa9SWenbin Song * Copyright (C) 2015, Freescale Semiconductor
5*8e728aa9SWenbin Song *
6*8e728aa9SWenbin Song * Mingkai Hu <Mingkai.hu@freescale.com>
7*8e728aa9SWenbin Song *
8*8e728aa9SWenbin Song * This file is licensed under the terms of the GNU General Public
9*8e728aa9SWenbin Song * License version 2.  This program is licensed "as is" without any
10*8e728aa9SWenbin Song * warranty of any kind, whether express or implied.
11*8e728aa9SWenbin Song */
12*8e728aa9SWenbin Song
13*8e728aa9SWenbin Song/include/ "fsl-ls1043a.dtsi"
14*8e728aa9SWenbin Song
15*8e728aa9SWenbin Song/ {
16*8e728aa9SWenbin Song	model = "LS1043A QDS Board";
17*8e728aa9SWenbin Song};
18*8e728aa9SWenbin Song
19*8e728aa9SWenbin Song&i2c0 {
20*8e728aa9SWenbin Song	status = "okay";
21*8e728aa9SWenbin Song	pca9547@77 {
22*8e728aa9SWenbin Song		compatible = "philips,pca9547";
23*8e728aa9SWenbin Song		reg = <0x77>;
24*8e728aa9SWenbin Song		#address-cells = <1>;
25*8e728aa9SWenbin Song		#size-cells = <0>;
26*8e728aa9SWenbin Song
27*8e728aa9SWenbin Song		i2c@0 {
28*8e728aa9SWenbin Song			#address-cells = <1>;
29*8e728aa9SWenbin Song			#size-cells = <0>;
30*8e728aa9SWenbin Song			reg = <0x0>;
31*8e728aa9SWenbin Song
32*8e728aa9SWenbin Song			rtc@68 {
33*8e728aa9SWenbin Song				compatible = "dallas,ds3232";
34*8e728aa9SWenbin Song				reg = <0x68>;
35*8e728aa9SWenbin Song				/* IRQ10_B */
36*8e728aa9SWenbin Song				interrupts = <0 150 0x4>;
37*8e728aa9SWenbin Song			};
38*8e728aa9SWenbin Song		};
39*8e728aa9SWenbin Song
40*8e728aa9SWenbin Song		i2c@2 {
41*8e728aa9SWenbin Song			#address-cells = <1>;
42*8e728aa9SWenbin Song			#size-cells = <0>;
43*8e728aa9SWenbin Song			reg = <0x2>;
44*8e728aa9SWenbin Song
45*8e728aa9SWenbin Song			ina220@40 {
46*8e728aa9SWenbin Song				compatible = "ti,ina220";
47*8e728aa9SWenbin Song				reg = <0x40>;
48*8e728aa9SWenbin Song				shunt-resistor = <1000>;
49*8e728aa9SWenbin Song			};
50*8e728aa9SWenbin Song
51*8e728aa9SWenbin Song			ina220@41 {
52*8e728aa9SWenbin Song				compatible = "ti,ina220";
53*8e728aa9SWenbin Song				reg = <0x41>;
54*8e728aa9SWenbin Song				shunt-resistor = <1000>;
55*8e728aa9SWenbin Song			};
56*8e728aa9SWenbin Song		};
57*8e728aa9SWenbin Song
58*8e728aa9SWenbin Song		i2c@3 {
59*8e728aa9SWenbin Song			#address-cells = <1>;
60*8e728aa9SWenbin Song			#size-cells = <0>;
61*8e728aa9SWenbin Song			reg = <0x3>;
62*8e728aa9SWenbin Song
63*8e728aa9SWenbin Song			eeprom@56 {
64*8e728aa9SWenbin Song				compatible = "at24,24c512";
65*8e728aa9SWenbin Song				reg = <0x56>;
66*8e728aa9SWenbin Song			};
67*8e728aa9SWenbin Song
68*8e728aa9SWenbin Song			eeprom@57 {
69*8e728aa9SWenbin Song				compatible = "at24,24c512";
70*8e728aa9SWenbin Song				reg = <0x57>;
71*8e728aa9SWenbin Song			};
72*8e728aa9SWenbin Song
73*8e728aa9SWenbin Song			adt7461a@4c {
74*8e728aa9SWenbin Song				compatible = "adt7461a";
75*8e728aa9SWenbin Song				reg = <0x4c>;
76*8e728aa9SWenbin Song			};
77*8e728aa9SWenbin Song		};
78*8e728aa9SWenbin Song	};
79*8e728aa9SWenbin Song};
80*8e728aa9SWenbin Song
81*8e728aa9SWenbin Song&ifc {
82*8e728aa9SWenbin Song	#address-cells = <2>;
83*8e728aa9SWenbin Song	#size-cells = <1>;
84*8e728aa9SWenbin Song	/* NOR, NAND Flashes and FPGA on board */
85*8e728aa9SWenbin Song	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
86*8e728aa9SWenbin Song		  0x2 0x0 0x0 0x7e800000 0x00010000
87*8e728aa9SWenbin Song		  0x3 0x0 0x0 0x7fb00000 0x00000100>;
88*8e728aa9SWenbin Song	status = "okay";
89*8e728aa9SWenbin Song
90*8e728aa9SWenbin Song	nor@0,0 {
91*8e728aa9SWenbin Song		#address-cells = <1>;
92*8e728aa9SWenbin Song		#size-cells = <1>;
93*8e728aa9SWenbin Song		compatible = "cfi-flash";
94*8e728aa9SWenbin Song		reg = <0x0 0x0 0x8000000>;
95*8e728aa9SWenbin Song		bank-width = <2>;
96*8e728aa9SWenbin Song		device-width = <1>;
97*8e728aa9SWenbin Song	};
98*8e728aa9SWenbin Song
99*8e728aa9SWenbin Song	nand@2,0 {
100*8e728aa9SWenbin Song		compatible = "fsl,ifc-nand";
101*8e728aa9SWenbin Song		#address-cells = <1>;
102*8e728aa9SWenbin Song		#size-cells = <1>;
103*8e728aa9SWenbin Song		reg = <0x1 0x0 0x10000>;
104*8e728aa9SWenbin Song	};
105*8e728aa9SWenbin Song
106*8e728aa9SWenbin Song	fpga: board-control@3,0 {
107*8e728aa9SWenbin Song		#address-cells = <1>;
108*8e728aa9SWenbin Song		#size-cells = <1>;
109*8e728aa9SWenbin Song		compatible = "simple-bus";
110*8e728aa9SWenbin Song		reg = <0x3 0x0 0x0000100>;
111*8e728aa9SWenbin Song		bank-width = <1>;
112*8e728aa9SWenbin Song		device-width = <1>;
113*8e728aa9SWenbin Song		ranges = <0 3 0 0x100>;
114*8e728aa9SWenbin Song	};
115*8e728aa9SWenbin Song};
116*8e728aa9SWenbin Song
117*8e728aa9SWenbin Song&duart0 {
118*8e728aa9SWenbin Song	status = "okay";
119*8e728aa9SWenbin Song};
120*8e728aa9SWenbin Song
121*8e728aa9SWenbin Song&duart1 {
122*8e728aa9SWenbin Song	status = "okay";
123*8e728aa9SWenbin Song};
124