14549e789STom Rini// SPDX-License-Identifier: GPL-2.0+ OR X11 28e728aa9SWenbin Song/* 38e728aa9SWenbin Song * Device Tree Include file for Freescale Layerscape-1043A family SoC. 48e728aa9SWenbin Song * 58e728aa9SWenbin Song * Copyright (C) 2015, Freescale Semiconductor 68e728aa9SWenbin Song * 78e728aa9SWenbin Song * Mingkai Hu <Mingkai.hu@freescale.com> 88e728aa9SWenbin Song */ 98e728aa9SWenbin Song 108e728aa9SWenbin Song/include/ "fsl-ls1043a.dtsi" 118e728aa9SWenbin Song 128e728aa9SWenbin Song/ { 138e728aa9SWenbin Song model = "LS1043A QDS Board"; 1473a5de4cSQianyu Gong aliases { 1573a5de4cSQianyu Gong spi0 = &qspi; 1673a5de4cSQianyu Gong spi1 = &dspi0; 1773a5de4cSQianyu Gong }; 1873a5de4cSQianyu Gong}; 1973a5de4cSQianyu Gong 2073a5de4cSQianyu Gong&dspi0 { 2173a5de4cSQianyu Gong bus-num = <0>; 2273a5de4cSQianyu Gong status = "okay"; 2373a5de4cSQianyu Gong 2473a5de4cSQianyu Gong dflash0: n25q128a { 2573a5de4cSQianyu Gong #address-cells = <1>; 2673a5de4cSQianyu Gong #size-cells = <1>; 2773a5de4cSQianyu Gong compatible = "spi-flash"; 2873a5de4cSQianyu Gong spi-max-frequency = <1000000>; /* input clock */ 292ef846e4SQianyu Gong spi-cpol; 302ef846e4SQianyu Gong spi-cpha; 312ef846e4SQianyu Gong reg = <0>; 3273a5de4cSQianyu Gong }; 3373a5de4cSQianyu Gong 3473a5de4cSQianyu Gong dflash1: sst25wf040b { 3573a5de4cSQianyu Gong #address-cells = <1>; 3673a5de4cSQianyu Gong #size-cells = <1>; 3773a5de4cSQianyu Gong compatible = "spi-flash"; 3873a5de4cSQianyu Gong spi-max-frequency = <3500000>; 392ef846e4SQianyu Gong spi-cpol; 402ef846e4SQianyu Gong spi-cpha; 4173a5de4cSQianyu Gong reg = <1>; 4273a5de4cSQianyu Gong }; 4373a5de4cSQianyu Gong 4473a5de4cSQianyu Gong dflash2: en25s64 { 4573a5de4cSQianyu Gong #address-cells = <1>; 4673a5de4cSQianyu Gong #size-cells = <1>; 4773a5de4cSQianyu Gong compatible = "spi-flash"; 4873a5de4cSQianyu Gong spi-max-frequency = <3500000>; 492ef846e4SQianyu Gong spi-cpol; 502ef846e4SQianyu Gong spi-cpha; 5173a5de4cSQianyu Gong reg = <2>; 5273a5de4cSQianyu Gong }; 5373a5de4cSQianyu Gong}; 5473a5de4cSQianyu Gong 5573a5de4cSQianyu Gong&qspi { 5673a5de4cSQianyu Gong bus-num = <0>; 5773a5de4cSQianyu Gong status = "okay"; 5873a5de4cSQianyu Gong 5973a5de4cSQianyu Gong qflash0: s25fl128s@0 { 6073a5de4cSQianyu Gong #address-cells = <1>; 6173a5de4cSQianyu Gong #size-cells = <1>; 6273a5de4cSQianyu Gong compatible = "spi-flash"; 6373a5de4cSQianyu Gong spi-max-frequency = <20000000>; 6473a5de4cSQianyu Gong reg = <0>; 6573a5de4cSQianyu Gong }; 668e728aa9SWenbin Song}; 678e728aa9SWenbin Song 688e728aa9SWenbin Song&i2c0 { 698e728aa9SWenbin Song status = "okay"; 708e728aa9SWenbin Song pca9547@77 { 718e728aa9SWenbin Song compatible = "philips,pca9547"; 728e728aa9SWenbin Song reg = <0x77>; 738e728aa9SWenbin Song #address-cells = <1>; 748e728aa9SWenbin Song #size-cells = <0>; 758e728aa9SWenbin Song 768e728aa9SWenbin Song i2c@0 { 778e728aa9SWenbin Song #address-cells = <1>; 788e728aa9SWenbin Song #size-cells = <0>; 798e728aa9SWenbin Song reg = <0x0>; 808e728aa9SWenbin Song 818e728aa9SWenbin Song rtc@68 { 828e728aa9SWenbin Song compatible = "dallas,ds3232"; 838e728aa9SWenbin Song reg = <0x68>; 848e728aa9SWenbin Song /* IRQ10_B */ 858e728aa9SWenbin Song interrupts = <0 150 0x4>; 868e728aa9SWenbin Song }; 878e728aa9SWenbin Song }; 888e728aa9SWenbin Song 898e728aa9SWenbin Song i2c@2 { 908e728aa9SWenbin Song #address-cells = <1>; 918e728aa9SWenbin Song #size-cells = <0>; 928e728aa9SWenbin Song reg = <0x2>; 938e728aa9SWenbin Song 948e728aa9SWenbin Song ina220@40 { 958e728aa9SWenbin Song compatible = "ti,ina220"; 968e728aa9SWenbin Song reg = <0x40>; 978e728aa9SWenbin Song shunt-resistor = <1000>; 988e728aa9SWenbin Song }; 998e728aa9SWenbin Song 1008e728aa9SWenbin Song ina220@41 { 1018e728aa9SWenbin Song compatible = "ti,ina220"; 1028e728aa9SWenbin Song reg = <0x41>; 1038e728aa9SWenbin Song shunt-resistor = <1000>; 1048e728aa9SWenbin Song }; 1058e728aa9SWenbin Song }; 1068e728aa9SWenbin Song 1078e728aa9SWenbin Song i2c@3 { 1088e728aa9SWenbin Song #address-cells = <1>; 1098e728aa9SWenbin Song #size-cells = <0>; 1108e728aa9SWenbin Song reg = <0x3>; 1118e728aa9SWenbin Song 1128e728aa9SWenbin Song eeprom@56 { 1138e728aa9SWenbin Song compatible = "at24,24c512"; 1148e728aa9SWenbin Song reg = <0x56>; 1158e728aa9SWenbin Song }; 1168e728aa9SWenbin Song 1178e728aa9SWenbin Song eeprom@57 { 1188e728aa9SWenbin Song compatible = "at24,24c512"; 1198e728aa9SWenbin Song reg = <0x57>; 1208e728aa9SWenbin Song }; 1218e728aa9SWenbin Song 1228e728aa9SWenbin Song adt7461a@4c { 1238e728aa9SWenbin Song compatible = "adt7461a"; 1248e728aa9SWenbin Song reg = <0x4c>; 1258e728aa9SWenbin Song }; 1268e728aa9SWenbin Song }; 1278e728aa9SWenbin Song }; 1288e728aa9SWenbin Song}; 1298e728aa9SWenbin Song 1308e728aa9SWenbin Song&ifc { 1318e728aa9SWenbin Song #address-cells = <2>; 1328e728aa9SWenbin Song #size-cells = <1>; 1338e728aa9SWenbin Song /* NOR, NAND Flashes and FPGA on board */ 1348e728aa9SWenbin Song ranges = <0x0 0x0 0x0 0x60000000 0x08000000 1354002eab2SHou Zhiqiang 0x1 0x0 0x0 0x7e800000 0x00010000 1364002eab2SHou Zhiqiang 0x2 0x0 0x0 0x7fb00000 0x00000100>; 1378e728aa9SWenbin Song status = "okay"; 1388e728aa9SWenbin Song 1398e728aa9SWenbin Song nor@0,0 { 1408e728aa9SWenbin Song #address-cells = <1>; 1418e728aa9SWenbin Song #size-cells = <1>; 1428e728aa9SWenbin Song compatible = "cfi-flash"; 1438e728aa9SWenbin Song reg = <0x0 0x0 0x8000000>; 1448e728aa9SWenbin Song bank-width = <2>; 1458e728aa9SWenbin Song device-width = <1>; 1468e728aa9SWenbin Song }; 1478e728aa9SWenbin Song 1484002eab2SHou Zhiqiang nand@1,0 { 1498e728aa9SWenbin Song compatible = "fsl,ifc-nand"; 1508e728aa9SWenbin Song #address-cells = <1>; 1518e728aa9SWenbin Song #size-cells = <1>; 1528e728aa9SWenbin Song reg = <0x1 0x0 0x10000>; 1538e728aa9SWenbin Song }; 1548e728aa9SWenbin Song 1554002eab2SHou Zhiqiang fpga: board-control@2,0 { 1568e728aa9SWenbin Song #address-cells = <1>; 1578e728aa9SWenbin Song #size-cells = <1>; 1588e728aa9SWenbin Song compatible = "simple-bus"; 1594002eab2SHou Zhiqiang reg = <0x2 0x0 0x0000100>; 1608e728aa9SWenbin Song bank-width = <1>; 1618e728aa9SWenbin Song device-width = <1>; 1624002eab2SHou Zhiqiang ranges = <0 2 0 0x100>; 1638e728aa9SWenbin Song }; 1648e728aa9SWenbin Song}; 1658e728aa9SWenbin Song 1668e728aa9SWenbin Song&duart0 { 1678e728aa9SWenbin Song status = "okay"; 1688e728aa9SWenbin Song}; 1698e728aa9SWenbin Song 1708e728aa9SWenbin Song&duart1 { 1718e728aa9SWenbin Song status = "okay"; 1728e728aa9SWenbin Song}; 1732970e14fSWenbin Song 1742970e14fSWenbin Song&lpuart0 { 1752970e14fSWenbin Song status = "okay"; 1762970e14fSWenbin Song}; 177*d9211656SPeng Ma 178*d9211656SPeng Ma&sata { 179*d9211656SPeng Ma status = "okay"; 180*d9211656SPeng Ma}; 181