1/* 2 * Copyright 2016 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/include/ "skeleton64.dtsi" 8 9/ { 10 compatible = "fsl,ls1012a"; 11 interrupt-parent = <&gic>; 12 13 sysclk: sysclk { 14 compatible = "fixed-clock"; 15 #clock-cells = <0>; 16 clock-frequency = <100000000>; 17 clock-output-names = "sysclk"; 18 }; 19 20 gic: interrupt-controller@1400000 { 21 compatible = "arm,gic-400"; 22 #interrupt-cells = <3>; 23 interrupt-controller; 24 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 25 <0x0 0x1402000 0 0x2000>, /* GICC */ 26 <0x0 0x1404000 0 0x2000>, /* GICH */ 27 <0x0 0x1406000 0 0x2000>; /* GICV */ 28 interrupts = <1 9 0xf08>; 29 }; 30 31 soc { 32 compatible = "simple-bus"; 33 #address-cells = <2>; 34 #size-cells = <2>; 35 ranges; 36 37 clockgen: clocking@1ee1000 { 38 compatible = "fsl,ls1012a-clockgen"; 39 reg = <0x0 0x1ee1000 0x0 0x1000>; 40 #clock-cells = <2>; 41 clocks = <&sysclk>; 42 }; 43 44 dspi0: dspi@2100000 { 45 compatible = "fsl,vf610-dspi"; 46 #address-cells = <1>; 47 #size-cells = <0>; 48 reg = <0x0 0x2100000 0x0 0x10000>; 49 interrupts = <0 64 0x4>; 50 clock-names = "dspi"; 51 clocks = <&clockgen 4 0>; 52 num-cs = <6>; 53 big-endian; 54 status = "disabled"; 55 }; 56 57 esdhc0: esdhc@1560000 { 58 compatible = "fsl,esdhc"; 59 reg = <0x0 0x1560000 0x0 0x10000>; 60 interrupts = <0 62 0x4>; 61 big-endian; 62 bus-width = <4>; 63 }; 64 65 esdhc1: esdhc@1580000 { 66 compatible = "fsl,esdhc"; 67 reg = <0x0 0x1580000 0x0 0x10000>; 68 interrupts = <0 65 0x4>; 69 big-endian; 70 non-removable; 71 bus-width = <4>; 72 }; 73 74 i2c0: i2c@2180000 { 75 compatible = "fsl,vf610-i2c"; 76 #address-cells = <1>; 77 #size-cells = <0>; 78 reg = <0x0 0x2180000 0x0 0x10000>; 79 interrupts = <0 56 0x4>; 80 clock-names = "i2c"; 81 clocks = <&clockgen 4 0>; 82 status = "disabled"; 83 }; 84 85 i2c1: i2c@2190000 { 86 compatible = "fsl,vf610-i2c"; 87 #address-cells = <1>; 88 #size-cells = <0>; 89 reg = <0x0 0x2190000 0x0 0x10000>; 90 interrupts = <0 57 0x4>; 91 clock-names = "i2c"; 92 clocks = <&clockgen 4 0>; 93 status = "disabled"; 94 }; 95 96 duart0: serial@21c0500 { 97 compatible = "fsl,ns16550", "ns16550a"; 98 reg = <0x00 0x21c0500 0x0 0x100>; 99 interrupts = <0 54 0x4>; 100 clocks = <&clockgen 4 0>; 101 }; 102 103 duart1: serial@21c0600 { 104 compatible = "fsl,ns16550", "ns16550a"; 105 reg = <0x00 0x21c0600 0x0 0x100>; 106 interrupts = <0 54 0x4>; 107 clocks = <&clockgen 4 0>; 108 }; 109 110 qspi: quadspi@1550000 { 111 compatible = "fsl,vf610-qspi"; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 reg = <0x0 0x1550000 0x0 0x10000>, 115 <0x0 0x40000000 0x0 0x4000000>; 116 reg-names = "QuadSPI", "QuadSPI-memory"; 117 num-cs = <1>; 118 big-endian; 119 status = "disabled"; 120 }; 121 122 pcie@3400000 { 123 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 124 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 125 0x00 0x03480000 0x0 0x40000 /* lut registers */ 126 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ 127 0x40 0x00000000 0x0 0x20000>; /* configuration space */ 128 reg-names = "dbi", "lut", "ctrl", "config"; 129 big-endian; 130 #address-cells = <3>; 131 #size-cells = <2>; 132 device_type = "pci"; 133 bus-range = <0x0 0xff>; 134 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */ 135 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 136 }; 137 138 usb0: usb2@8600000 { 139 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 140 reg = <0x0 0x8600000 0x0 0x1000>; 141 interrupts = <0 139 0x4>; 142 dr_mode = "host"; 143 fsl,usb-erratum-a005697; 144 }; 145 146 usb1: usb3@2f00000 { 147 compatible = "fsl,layerscape-dwc3"; 148 reg = <0x0 0x2f00000 0x0 0x10000>; 149 interrupts = <0 61 0x4>; 150 dr_mode = "host"; 151 }; 152 }; 153}; 154