1/* 2 * Copyright 2016 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/include/ "skeleton64.dtsi" 8 9/ { 10 compatible = "fsl,ls1012a"; 11 interrupt-parent = <&gic>; 12 cpus { 13 #address-cells = <2>; 14 #size-cells = <0>; 15 16 cpu0: cpu@0 { 17 device_type = "cpu"; 18 compatible = "arm,cortex-a53"; 19 reg = <0x0 0x0>; 20 clocks = <&clockgen 1 0>; 21 }; 22 23 }; 24 25 sysclk: sysclk { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <100000000>; 29 clock-output-names = "sysclk"; 30 }; 31 32 gic: interrupt-controller@1400000 { 33 compatible = "arm,gic-400"; 34 #interrupt-cells = <3>; 35 interrupt-controller; 36 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 37 <0x0 0x1402000 0 0x2000>, /* GICC */ 38 <0x0 0x1404000 0 0x2000>, /* GICH */ 39 <0x0 0x1406000 0 0x2000>; /* GICV */ 40 interrupts = <1 9 0xf08>; 41 }; 42 43 soc { 44 compatible = "simple-bus"; 45 #address-cells = <2>; 46 #size-cells = <2>; 47 ranges; 48 49 clockgen: clocking@1ee1000 { 50 compatible = "fsl,ls1012a-clockgen"; 51 reg = <0x0 0x1ee1000 0x0 0x1000>; 52 #clock-cells = <2>; 53 clocks = <&sysclk>; 54 }; 55 56 dspi0: dspi@2100000 { 57 compatible = "fsl,vf610-dspi"; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 reg = <0x0 0x2100000 0x0 0x10000>; 61 interrupts = <0 64 0x4>; 62 clock-names = "dspi"; 63 clocks = <&clockgen 4 0>; 64 num-cs = <6>; 65 big-endian; 66 status = "disabled"; 67 }; 68 69 70 i2c0: i2c@2180000 { 71 compatible = "fsl,vf610-i2c"; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 reg = <0x0 0x2180000 0x0 0x10000>; 75 interrupts = <0 56 0x4>; 76 clock-names = "i2c"; 77 clocks = <&clockgen 4 0>; 78 status = "disabled"; 79 }; 80 81 i2c1: i2c@2190000 { 82 compatible = "fsl,vf610-i2c"; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 reg = <0x0 0x2190000 0x0 0x10000>; 86 interrupts = <0 57 0x4>; 87 clock-names = "i2c"; 88 clocks = <&clockgen 4 0>; 89 status = "disabled"; 90 }; 91 92 duart0: serial@21c0500 { 93 compatible = "fsl,ns16550", "ns16550a"; 94 reg = <0x00 0x21c0500 0x0 0x100>; 95 interrupts = <0 54 0x4>; 96 clocks = <&clockgen 4 0>; 97 }; 98 99 duart1: serial@21c0600 { 100 compatible = "fsl,ns16550", "ns16550a"; 101 reg = <0x00 0x21c0600 0x0 0x100>; 102 interrupts = <0 54 0x4>; 103 clocks = <&clockgen 4 0>; 104 }; 105 106 qspi: quadspi@1550000 { 107 compatible = "fsl,vf610-qspi"; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 reg = <0x0 0x1550000 0x0 0x10000>, 111 <0x0 0x40000000 0x0 0x4000000>; 112 reg-names = "QuadSPI", "QuadSPI-memory"; 113 num-cs = <2>; 114 big-endian; 115 status = "disabled"; 116 }; 117 118 }; 119}; 120