1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2017-2018 NXP 4 */ 5 6/dts-v1/; 7 8#include "fsl-imx8qxp.dtsi" 9 10/ { 11 model = "Freescale i.MX8QXP MEK"; 12 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; 13 14 chosen { 15 bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; 16 stdout-path = &lpuart0; 17 }; 18 19 regulators { 20 compatible = "simple-bus"; 21 22 reg_usdhc2_vmmc: usdhc2-vmmc { 23 compatible = "regulator-fixed"; 24 regulator-name = "SD1_SPWR"; 25 regulator-min-microvolt = <3000000>; 26 regulator-max-microvolt = <3000000>; 27 gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; 28 off-on-delay = <3480>; 29 enable-active-high; 30 }; 31 }; 32}; 33 34&iomuxc { 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_hog>; 37 38 imx8qxp-mek { 39 pinctrl_hog: hoggrp { 40 fsl,pins = < 41 SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c 42 SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 43 >; 44 }; 45 46 pinctrl_ioexp_rst: ioexp-rst-grp { 47 fsl,pins = < 48 SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 49 >; 50 }; 51 52 pinctrl_fec1: fec1grp { 53 fsl,pins = < 54 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 55 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 56 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 57 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 58 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 59 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 60 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 61 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 62 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 63 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 64 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 65 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 66 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 67 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 68 >; 69 }; 70 71 pinctrl_fec2: fec2grp { 72 fsl,pins = < 73 SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000048 74 SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000048 75 SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000048 76 SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000048 77 SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000048 78 SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000048 79 SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000048 80 SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000048 81 SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000048 82 SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000048 83 SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000048 84 SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000048 85 >; 86 }; 87 88 pinctrl_lpi2c1: lpi2c1grp { 89 fsl,pins = < 90 SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 91 SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 92 >; 93 }; 94 95 pinctrl_lpuart0: lpuart0grp { 96 fsl,pins = < 97 SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 98 SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 99 >; 100 }; 101 102 pinctrl_usdhc1: usdhc1grp { 103 fsl,pins = < 104 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 105 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 106 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 107 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 108 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 109 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 110 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 111 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 112 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 113 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 114 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 115 >; 116 }; 117 118 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 119 fsl,pins = < 120 SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 121 SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 122 SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 123 >; 124 }; 125 126 pinctrl_usdhc2: usdhc2grp { 127 fsl,pins = < 128 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 129 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 130 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 131 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 132 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 133 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 134 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 135 >; 136 }; 137 }; 138}; 139 140&A35_0 { 141 u-boot,dm-pre-reloc; 142}; 143 144&lpuart0 { 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_lpuart0>; 147 status = "okay"; 148}; 149 150&i2c1 { 151 clock-frequency = <100000>; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; 154 status = "okay"; 155 156 i2cswitch@71 { 157 compatible = "nxp,pca9646"; 158 reg = <0x71>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 162 163 bb_i2c1: i2c@0 { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 reg = <0x0>; 167 }; 168 169 mfi_i2c1: i2c@1 { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 reg = <0x1>; 173 }; 174 175 i2cexp1_i2c1: i2c@2 { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 reg = <0x2>; 179 }; 180 181 i2cexp2_i2c1: i2c@3 { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 reg = <0x3>; 185 186 pca9557_a: gpio@1a { 187 compatible = "nxp,pca9557"; 188 reg = <0x1a>; 189 gpio-controller; 190 #gpio-cells = <2>; 191 }; 192 pca9557_b: gpio@1d { 193 compatible = "nxp,pca9557"; 194 reg = <0x1d>; 195 gpio-controller; 196 #gpio-cells = <2>; 197 }; 198 }; 199 }; 200}; 201 202&usdhc1 { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_usdhc1>; 205 bus-width = <8>; 206 non-removable; 207 status = "okay"; 208}; 209 210&usdhc2 { 211 pinctrl-names = "default"; 212 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 213 bus-width = <4>; 214 cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 215 wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; 216 vmmc-supply = <®_usdhc2_vmmc>; 217 status = "okay"; 218}; 219 220&fec1 { 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_fec1>; 223 phy-mode = "rgmii"; 224 phy-handle = <ðphy0>; 225 fsl,ar8031-phy-fixup; 226 fsl,magic-packet; 227 status = "okay"; 228 phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>; 229 phy-reset-duration = <10>; 230 231 mdio { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 235 ethphy0: ethernet-phy@0 { 236 compatible = "ethernet-phy-ieee802.3-c22"; 237 reg = <0>; 238 }; 239 ethphy1: ethernet-phy@1 { 240 compatible = "ethernet-phy-ieee802.3-c22"; 241 reg = <1>; 242 }; 243 }; 244}; 245