1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2017-2018 NXP 4 */ 5 6/dts-v1/; 7 8#include "fsl-imx8qxp.dtsi" 9 10/ { 11 model = "Freescale i.MX8QXP MEK"; 12 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; 13 14 chosen { 15 bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; 16 stdout-path = &lpuart0; 17 }; 18 19 regulators { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 reg_usdhc2_vmmc: usdhc2-vmmc { 25 compatible = "regulator-fixed"; 26 regulator-name = "SD1_SPWR"; 27 regulator-min-microvolt = <3000000>; 28 regulator-max-microvolt = <3000000>; 29 gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; 30 off-on-delay = <3480>; 31 enable-active-high; 32 }; 33 }; 34}; 35 36&iomuxc { 37 pinctrl-names = "default"; 38 pinctrl-0 = <&pinctrl_hog>; 39 40 imx8qxp-mek { 41 pinctrl_hog: hoggrp { 42 fsl,pins = < 43 SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c 44 SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 45 >; 46 }; 47 48 pinctrl_ioexp_rst: ioexp-rst-grp { 49 fsl,pins = < 50 SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 51 >; 52 }; 53 54 pinctrl_fec1: fec1grp { 55 fsl,pins = < 56 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 57 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 58 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 59 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 60 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 61 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 62 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 63 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 64 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 65 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 66 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 67 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 68 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 69 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 70 >; 71 }; 72 73 pinctrl_fec2: fec2grp { 74 fsl,pins = < 75 SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000048 76 SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000048 77 SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000048 78 SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000048 79 SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000048 80 SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000048 81 SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000048 82 SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000048 83 SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000048 84 SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000048 85 SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000048 86 SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000048 87 >; 88 }; 89 90 pinctrl_lpi2c1: lpi2c1grp { 91 fsl,pins = < 92 SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 93 SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 94 >; 95 }; 96 97 pinctrl_lpuart0: lpuart0grp { 98 fsl,pins = < 99 SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 100 SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 101 >; 102 }; 103 104 pinctrl_usdhc1: usdhc1grp { 105 fsl,pins = < 106 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 107 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 108 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 109 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 110 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 111 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 112 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 113 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 114 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 115 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 116 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 117 >; 118 }; 119 120 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 121 fsl,pins = < 122 SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 123 SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 124 SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 125 >; 126 }; 127 128 pinctrl_usdhc2: usdhc2grp { 129 fsl,pins = < 130 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 131 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 132 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 133 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 134 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 135 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 136 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 137 >; 138 }; 139 }; 140}; 141 142&A35_0 { 143 u-boot,dm-pre-reloc; 144}; 145 146&lpuart0 { 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_lpuart0>; 149 status = "okay"; 150}; 151 152&i2c1 { 153 clock-frequency = <100000>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; 156 status = "okay"; 157 158 i2cswitch@71 { 159 compatible = "nxp,pca9646"; 160 reg = <0x71>; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 164 165 bb_i2c1: i2c@0 { 166 #address-cells = <1>; 167 #size-cells = <0>; 168 reg = <0x0>; 169 }; 170 171 mfi_i2c1: i2c@1 { 172 #address-cells = <1>; 173 #size-cells = <0>; 174 reg = <0x1>; 175 }; 176 177 i2cexp1_i2c1: i2c@2 { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 reg = <0x2>; 181 }; 182 183 i2cexp2_i2c1: i2c@3 { 184 #address-cells = <1>; 185 #size-cells = <0>; 186 reg = <0x3>; 187 188 pca9557_a: gpio@1a { 189 compatible = "nxp,pca9557"; 190 reg = <0x1a>; 191 gpio-controller; 192 #gpio-cells = <2>; 193 }; 194 pca9557_b: gpio@1d { 195 compatible = "nxp,pca9557"; 196 reg = <0x1d>; 197 gpio-controller; 198 #gpio-cells = <2>; 199 }; 200 }; 201 }; 202}; 203 204&usdhc1 { 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_usdhc1>; 207 bus-width = <8>; 208 non-removable; 209 status = "okay"; 210}; 211 212&usdhc2 { 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 215 bus-width = <4>; 216 cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 217 wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; 218 vmmc-supply = <®_usdhc2_vmmc>; 219 status = "okay"; 220}; 221 222&fec1 { 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_fec1>; 225 phy-mode = "rgmii"; 226 phy-handle = <ðphy0>; 227 fsl,ar8031-phy-fixup; 228 fsl,magic-packet; 229 status = "okay"; 230 phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>; 231 phy-reset-duration = <10>; 232 233 mdio { 234 #address-cells = <1>; 235 #size-cells = <0>; 236 237 ethphy0: ethernet-phy@0 { 238 compatible = "ethernet-phy-ieee802.3-c22"; 239 reg = <0>; 240 }; 241 ethphy1: ethernet-phy@1 { 242 compatible = "ethernet-phy-ieee802.3-c22"; 243 reg = <1>; 244 }; 245 }; 246}; 247