1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2017-2018 NXP
4 */
5
6/dts-v1/;
7
8#include "fsl-imx8qxp.dtsi"
9#include "fsl-imx8qxp-mek-u-boot.dtsi"
10
11/ {
12	model = "Freescale i.MX8QXP MEK";
13	compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
14
15	chosen {
16		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
17		stdout-path = &lpuart0;
18	};
19
20	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
21		compatible = "regulator-fixed";
22		regulator-name = "SD1_SPWR";
23		regulator-min-microvolt = <3000000>;
24		regulator-max-microvolt = <3000000>;
25		gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
26		off-on-delay = <3480>;
27		enable-active-high;
28	};
29};
30
31&iomuxc {
32	pinctrl-names = "default";
33	pinctrl-0 = <&pinctrl_hog>;
34
35	imx8qxp-mek {
36		pinctrl_hog: hoggrp {
37			fsl,pins = <
38				SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0	0x0600004c
39				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
40			>;
41		};
42
43		pinctrl_ioexp_rst: ioexp-rst-grp {
44			fsl,pins = <
45				SC_P_SPI2_SDO_LSIO_GPIO1_IO01	0x06000021
46			>;
47		};
48
49		pinctrl_fec1: fec1grp {
50			fsl,pins = <
51				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000048
52				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000048
53				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000048
54				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000048
55				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000048
56				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000048
57				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000048
58				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000048
59				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000048
60				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000048
61				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000048
62				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000048
63				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000048
64				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000048
65			>;
66		};
67
68		pinctrl_fec2: fec2grp {
69			fsl,pins = <
70				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x06000048
71				SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x06000048
72				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x06000048
73				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x06000048
74				SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x06000048
75				SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x06000048
76				SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x06000048
77				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x06000048
78				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x06000048
79				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x06000048
80				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x06000048
81				SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x06000048
82			>;
83		};
84
85		pinctrl_lpi2c1: lpi2c1grp {
86			fsl,pins = <
87				SC_P_USB_SS3_TC1_ADMA_I2C1_SCL	0x06000021
88				SC_P_USB_SS3_TC3_ADMA_I2C1_SDA	0x06000021
89			>;
90		};
91
92		pinctrl_lpuart0: lpuart0grp {
93			fsl,pins = <
94				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
95				SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
96			>;
97		};
98
99		pinctrl_usdhc1: usdhc1grp {
100			fsl,pins = <
101				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
102				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
103				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
104				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
105				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
106				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
107				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
108				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
109				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
110				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
111				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
112			>;
113		};
114
115		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
116			fsl,pins = <
117				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x00000021
118				SC_P_USDHC1_WP_LSIO_GPIO4_IO21		0x00000021
119				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x00000021
120			>;
121		};
122
123		pinctrl_usdhc2: usdhc2grp {
124			fsl,pins = <
125				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
126				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
127				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
128				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
129				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
130				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
131				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
132			>;
133		};
134	};
135};
136
137&A35_0 {
138	u-boot,dm-pre-reloc;
139};
140
141&lpuart0 {
142	pinctrl-names = "default";
143	pinctrl-0 = <&pinctrl_lpuart0>;
144	status = "okay";
145};
146
147&i2c1 {
148	clock-frequency = <100000>;
149	pinctrl-names = "default";
150	pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
151	status = "okay";
152
153	i2cswitch@71 {
154		compatible = "nxp,pca9646";
155		reg = <0x71>;
156		#address-cells = <1>;
157		#size-cells = <0>;
158		reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
159
160		bb_i2c1: i2c@0 {
161			#address-cells = <1>;
162			#size-cells = <0>;
163			reg = <0x0>;
164		};
165
166		mfi_i2c1: i2c@1 {
167			#address-cells = <1>;
168			#size-cells = <0>;
169			reg = <0x1>;
170		};
171
172		i2cexp1_i2c1: i2c@2 {
173			#address-cells = <1>;
174			#size-cells = <0>;
175			reg = <0x2>;
176		};
177
178		i2cexp2_i2c1: i2c@3 {
179			#address-cells = <1>;
180			#size-cells = <0>;
181			reg = <0x3>;
182
183			pca9557_a: gpio@1a {
184				compatible = "nxp,pca9557";
185				reg = <0x1a>;
186				gpio-controller;
187				#gpio-cells = <2>;
188			};
189			pca9557_b: gpio@1d {
190				compatible = "nxp,pca9557";
191				reg = <0x1d>;
192				gpio-controller;
193				#gpio-cells = <2>;
194			};
195		};
196	};
197};
198
199&usdhc1 {
200	pinctrl-names = "default";
201	pinctrl-0 = <&pinctrl_usdhc1>;
202	bus-width = <8>;
203	non-removable;
204	status = "okay";
205};
206
207&usdhc2 {
208	pinctrl-names = "default";
209	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
210	bus-width = <4>;
211	cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
212	wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
213	vmmc-supply = <&reg_usdhc2_vmmc>;
214	status = "okay";
215};
216
217&fec1 {
218	pinctrl-names = "default";
219	pinctrl-0 = <&pinctrl_fec1>;
220	phy-mode = "rgmii";
221	phy-handle = <&ethphy0>;
222	fsl,ar8031-phy-fixup;
223	fsl,magic-packet;
224	status = "okay";
225	phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>;
226	phy-reset-duration = <10>;
227
228	mdio {
229		#address-cells = <1>;
230		#size-cells = <0>;
231
232		ethphy0: ethernet-phy@0 {
233			compatible = "ethernet-phy-ieee802.3-c22";
234			reg = <0>;
235		};
236		ethphy1: ethernet-phy@1 {
237			compatible = "ethernet-phy-ieee802.3-c22";
238			reg = <1>;
239		};
240	};
241};
242