1/* 2 * Samsung Exynos7420 SoC device tree source 3 * 4 * Copyright (c) 2016 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/dts-v1/; 11#include "skeleton.dtsi" 12#include <dt-bindings/clock/exynos7420-clk.h> 13/ { 14 compatible = "samsung,exynos7420"; 15 16 fin_pll: xxti { 17 compatible = "fixed-clock"; 18 clock-output-names = "fin_pll"; 19 u-boot,dm-pre-reloc; 20 #clock-cells = <0>; 21 }; 22 23 clock_topc: clock-controller@10570000 { 24 compatible = "samsung,exynos7-clock-topc"; 25 reg = <0x10570000 0x10000>; 26 u-boot,dm-pre-reloc; 27 #clock-cells = <1>; 28 clocks = <&fin_pll>; 29 clock-names = "fin_pll"; 30 }; 31 32 clock_top0: clock-controller@105d0000 { 33 compatible = "samsung,exynos7-clock-top0"; 34 reg = <0x105d0000 0xb000>; 35 u-boot,dm-pre-reloc; 36 #clock-cells = <1>; 37 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 38 <&clock_topc DOUT_SCLK_BUS1_PLL>, 39 <&clock_topc DOUT_SCLK_CC_PLL>, 40 <&clock_topc DOUT_SCLK_MFC_PLL>; 41 clock-names = "fin_pll", "dout_sclk_bus0_pll", 42 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 43 "dout_sclk_mfc_pll"; 44 }; 45 46 clock_peric1: clock-controller@14c80000 { 47 compatible = "samsung,exynos7-clock-peric1"; 48 reg = <0x14c80000 0xd00>; 49 u-boot,dm-pre-reloc; 50 #clock-cells = <1>; 51 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, 52 <&clock_top0 CLK_SCLK_UART1>, 53 <&clock_top0 CLK_SCLK_UART2>, 54 <&clock_top0 CLK_SCLK_UART3>; 55 clock-names = "fin_pll", "dout_aclk_peric1_66", 56 "sclk_uart1", "sclk_uart2", "sclk_uart3"; 57 }; 58 59 pinctrl@13470000 { 60 compatible = "samsung,exynos7420-pinctrl"; 61 reg = <0x13470000 0x1000>; 62 u-boot,dm-pre-reloc; 63 64 serial2_bus: serial2-bus { 65 samsung,pins = "gpd1-4", "gpd1-5"; 66 samsung,pin-function = <2>; 67 samsung,pin-pud = <3>; 68 samsung,pin-drv = <0>; 69 u-boot,dm-pre-reloc; 70 }; 71 }; 72 73 serial@14C30000 { 74 compatible = "samsung,exynos4210-uart"; 75 reg = <0x14C30000 0x100>; 76 u-boot,dm-pre-reloc; 77 clocks = <&clock_peric1 PCLK_UART2>, 78 <&clock_peric1 SCLK_UART2>; 79 clock-names = "uart", "clk_uart_baud0"; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&serial2_bus>; 82 }; 83}; 84