xref: /openbmc/u-boot/arch/arm/dts/exynos7420.dtsi (revision e39448e8)
1*e39448e8SThomas Abraham/*
2*e39448e8SThomas Abraham * Samsung Exynos7420 SoC device tree source
3*e39448e8SThomas Abraham *
4*e39448e8SThomas Abraham * Copyright (c) 2016 Samsung Electronics Co., Ltd.
5*e39448e8SThomas Abraham *		http://www.samsung.com
6*e39448e8SThomas Abraham *
7*e39448e8SThomas Abraham * SPDX-License-Identifier:	GPL-2.0+
8*e39448e8SThomas Abraham */
9*e39448e8SThomas Abraham
10*e39448e8SThomas Abraham/dts-v1/;
11*e39448e8SThomas Abraham#include "skeleton.dtsi"
12*e39448e8SThomas Abraham#include <dt-bindings/clock/exynos7420-clk.h>
13*e39448e8SThomas Abraham/ {
14*e39448e8SThomas Abraham	compatible = "samsung,exynos7420";
15*e39448e8SThomas Abraham
16*e39448e8SThomas Abraham	fin_pll: xxti {
17*e39448e8SThomas Abraham		compatible = "fixed-clock";
18*e39448e8SThomas Abraham		clock-output-names = "fin_pll";
19*e39448e8SThomas Abraham		u-boot,dm-pre-reloc;
20*e39448e8SThomas Abraham		#clock-cells = <0>;
21*e39448e8SThomas Abraham	};
22*e39448e8SThomas Abraham
23*e39448e8SThomas Abraham	clock_topc: clock-controller@10570000 {
24*e39448e8SThomas Abraham		compatible = "samsung,exynos7-clock-topc";
25*e39448e8SThomas Abraham		reg = <0x10570000 0x10000>;
26*e39448e8SThomas Abraham		u-boot,dm-pre-reloc;
27*e39448e8SThomas Abraham		#clock-cells = <1>;
28*e39448e8SThomas Abraham		clocks = <&fin_pll>;
29*e39448e8SThomas Abraham		clock-names = "fin_pll";
30*e39448e8SThomas Abraham	};
31*e39448e8SThomas Abraham
32*e39448e8SThomas Abraham	clock_top0: clock-controller@105d0000 {
33*e39448e8SThomas Abraham		compatible = "samsung,exynos7-clock-top0";
34*e39448e8SThomas Abraham		reg = <0x105d0000 0xb000>;
35*e39448e8SThomas Abraham		u-boot,dm-pre-reloc;
36*e39448e8SThomas Abraham		#clock-cells = <1>;
37*e39448e8SThomas Abraham		clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
38*e39448e8SThomas Abraham			 <&clock_topc DOUT_SCLK_BUS1_PLL>,
39*e39448e8SThomas Abraham			 <&clock_topc DOUT_SCLK_CC_PLL>,
40*e39448e8SThomas Abraham			 <&clock_topc DOUT_SCLK_MFC_PLL>;
41*e39448e8SThomas Abraham		clock-names = "fin_pll", "dout_sclk_bus0_pll",
42*e39448e8SThomas Abraham			      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
43*e39448e8SThomas Abraham			      "dout_sclk_mfc_pll";
44*e39448e8SThomas Abraham	};
45*e39448e8SThomas Abraham
46*e39448e8SThomas Abraham	clock_peric1: clock-controller@14c80000 {
47*e39448e8SThomas Abraham		compatible = "samsung,exynos7-clock-peric1";
48*e39448e8SThomas Abraham		reg = <0x14c80000 0xd00>;
49*e39448e8SThomas Abraham		u-boot,dm-pre-reloc;
50*e39448e8SThomas Abraham		#clock-cells = <1>;
51*e39448e8SThomas Abraham		clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
52*e39448e8SThomas Abraham			 <&clock_top0 CLK_SCLK_UART1>,
53*e39448e8SThomas Abraham			 <&clock_top0 CLK_SCLK_UART2>,
54*e39448e8SThomas Abraham			 <&clock_top0 CLK_SCLK_UART3>;
55*e39448e8SThomas Abraham		clock-names = "fin_pll", "dout_aclk_peric1_66",
56*e39448e8SThomas Abraham			      "sclk_uart1", "sclk_uart2", "sclk_uart3";
57*e39448e8SThomas Abraham	};
58*e39448e8SThomas Abraham
59*e39448e8SThomas Abraham	pinctrl@13470000 {
60*e39448e8SThomas Abraham		compatible = "samsung,exynos7420-pinctrl";
61*e39448e8SThomas Abraham		reg = <0x13470000 0x1000>;
62*e39448e8SThomas Abraham		u-boot,dm-pre-reloc;
63*e39448e8SThomas Abraham
64*e39448e8SThomas Abraham		serial2_bus: serial2-bus {
65*e39448e8SThomas Abraham			samsung,pins = "gpd1-4", "gpd1-5";
66*e39448e8SThomas Abraham			samsung,pin-function = <2>;
67*e39448e8SThomas Abraham			samsung,pin-pud = <3>;
68*e39448e8SThomas Abraham			samsung,pin-drv = <0>;
69*e39448e8SThomas Abraham			u-boot,dm-pre-reloc;
70*e39448e8SThomas Abraham		};
71*e39448e8SThomas Abraham	};
72*e39448e8SThomas Abraham
73*e39448e8SThomas Abraham	serial@14C30000 {
74*e39448e8SThomas Abraham		compatible = "samsung,exynos4210-uart";
75*e39448e8SThomas Abraham		reg = <0x14C30000 0x100>;
76*e39448e8SThomas Abraham		u-boot,dm-pre-reloc;
77*e39448e8SThomas Abraham		clocks = <&clock_peric1 PCLK_UART2>,
78*e39448e8SThomas Abraham			 <&clock_peric1 SCLK_UART2>;
79*e39448e8SThomas Abraham		clock-names = "uart", "clk_uart_baud0";
80*e39448e8SThomas Abraham		pinctrl-names = "default";
81*e39448e8SThomas Abraham		pinctrl-0 = <&serial2_bus>;
82*e39448e8SThomas Abraham	};
83*e39448e8SThomas Abraham};
84