1/*
2 * SAMSUNG/GOOGLE Peach-Pit board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 *		http://www.samsung.com
6 *
7 * SPDX-License-Identifier:	GPL-2.0+
8 */
9
10/dts-v1/;
11#include "exynos54xx.dtsi"
12
13/ {
14	model = "Samsung/Google Peach Pit board based on Exynos5420";
15
16	compatible = "google,pit-rev#", "google,pit",
17		"google,peach", "samsung,exynos5420", "samsung,exynos5";
18
19	config {
20		google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
21		hwid = "PIT TEST A-A 7848";
22		lazy-init = <1>;
23	};
24
25	aliases {
26		serial0 = "/serial@12C30000";
27		console = "/serial@12C30000";
28		pmic = "/i2c@12ca0000";
29	};
30
31	dmc {
32		mem-manuf = "samsung";
33		mem-type = "ddr3";
34		clock-frequency = <800000000>;
35		arm-frequency = <900000000>;
36	};
37
38	tmu@10060000 {
39		samsung,min-temp	= <25>;
40		samsung,max-temp	= <125>;
41		samsung,start-warning	= <95>;
42		samsung,start-tripping	= <105>;
43		samsung,hw-tripping	= <110>;
44		samsung,efuse-min-value	= <40>;
45		samsung,efuse-value	= <55>;
46		samsung,efuse-max-value	= <100>;
47		samsung,slope		= <274761730>;
48		samsung,dc-value	= <25>;
49	};
50
51	/* MAX77802 is on i2c bus 4 */
52	i2c@12ca0000 {
53		clock-frequency = <400000>;
54		power-regulator@9 {
55			compatible = "maxim,max77802-pmic";
56			reg = <0x9>;
57		};
58	};
59
60	i2c@12cd0000 { /* i2c7 */
61		clock-frequency = <100000>;
62	       soundcodec@20 {
63	              reg = <0x20>;
64	              compatible = "maxim,max98090-codec";
65	       };
66
67	        edp-lvds-bridge@48 {
68	                compatible = "parade,ps8625";
69	                reg = <0x48>;
70	        };
71	};
72
73        sound@3830000 {
74                samsung,codec-type = "max98090";
75        };
76
77	i2c@12e10000 { /* i2c9 */
78		clock-frequency = <400000>;
79                tpm@20 {
80                        compatible = "infineon,slb9645-tpm";
81                        reg = <0x20>;
82		};
83	};
84
85	spi@12d30000 { /* spi1 */
86		spi-max-frequency = <50000000>;
87		firmware_storage_spi: flash@0 {
88			compatible = "spi-flash";
89			reg = <0>;
90
91			/*
92			 * A region for the kernel to store a panic event
93			 * which the firmware will add to the log.
94			*/
95			elog-panic-event-offset = <0x01e00000 0x100000>;
96
97			elog-shrink-size = <0x400>;
98			elog-full-threshold = <0xc00>;
99		};
100	};
101
102	spi@12d40000 { /* spi2 */
103		spi-max-frequency = <4000000>;
104		spi-deactivate-delay = <200>;
105		cros_ec: cros-ec@0 {
106			reg = <0>;
107			compatible = "google,cros-ec";
108			spi-half-duplex;
109			spi-max-timeout-ms = <1100>;
110			spi-frame-header = <0xec>;
111			ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
112
113			/*
114			 * This describes the flash memory within the EC. Note
115			 * that the STM32L flash erases to 0, not 0xff.
116			 */
117			#address-cells = <1>;
118			#size-cells = <1>;
119			flash@8000000 {
120				reg = <0x08000000 0x20000>;
121				erase-value = <0>;
122			};
123		};
124	};
125
126	xhci@12000000 {
127		samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
128	};
129
130	xhci@12400000 {
131		samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
132	};
133
134	fimd@14400000 {
135		samsung,vl-freq = <60>;
136		samsung,vl-col = <1366>;
137		samsung,vl-row = <768>;
138		samsung,vl-width = <1366>;
139		samsung,vl-height = <768>;
140
141		samsung,vl-clkp;
142		samsung,vl-dp;
143		samsung,vl-bpix = <4>;
144
145		samsung,vl-hspw = <32>;
146		samsung,vl-hbpd = <40>;
147		samsung,vl-hfpd = <40>;
148		samsung,vl-vspw = <6>;
149		samsung,vl-vbpd = <10>;
150		samsung,vl-vfpd = <12>;
151		samsung,vl-cmd-allow-len = <0xf>;
152
153		samsung,winid = <3>;
154		samsung,interface-mode = <1>;
155		samsung,dp-enabled = <1>;
156		samsung,dual-lcd-enabled = <0>;
157	};
158};
159
160#include "cros-ec-keyboard.dtsi"
161