1/*
2 * SAMSUNG/GOOGLE Peach-Pit board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 *		http://www.samsung.com
6 *
7 * SPDX-License-Identifier:	GPL-2.0+
8 */
9
10/dts-v1/;
11#include "exynos54xx.dtsi"
12#include <dt-bindings/clock/maxim,max77802.h>
13#include <dt-bindings/regulator/maxim,max77802.h>
14
15/ {
16	model = "Samsung/Google Peach Pit board based on Exynos5420";
17
18	compatible = "google,pit-rev#", "google,pit",
19		"google,peach", "samsung,exynos5420", "samsung,exynos5";
20
21	config {
22		google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
23		hwid = "PIT TEST A-A 7848";
24		lazy-init = <1>;
25	};
26
27	aliases {
28		serial0 = "/serial@12C30000";
29		console = "/serial@12C30000";
30		pmic = "/i2c@12CA0000";
31		i2c104 = &i2c_tunnel;
32	};
33
34	backlight: backlight {
35		compatible = "pwm-backlight";
36		pwms = <&pwm 0 1000000 0>;
37		brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
38		default-brightness-level = <7>;
39		power-supply = <&tps65090_fet1>;
40	};
41
42	dmc {
43		mem-manuf = "samsung";
44		mem-type = "ddr3";
45		clock-frequency = <800000000>;
46		arm-frequency = <900000000>;
47	};
48
49	tmu@10060000 {
50		samsung,min-temp	= <25>;
51		samsung,max-temp	= <125>;
52		samsung,start-warning	= <95>;
53		samsung,start-tripping	= <105>;
54		samsung,hw-tripping	= <110>;
55		samsung,efuse-min-value	= <40>;
56		samsung,efuse-value	= <55>;
57		samsung,efuse-max-value	= <100>;
58		samsung,slope		= <274761730>;
59		samsung,dc-value	= <25>;
60	};
61
62	/* MAX77802 is on i2c bus 4 */
63	i2c@12CA0000 {
64		clock-frequency = <400000>;
65		power-regulator@9 {
66			compatible = "maxim,max77802-pmic";
67			reg = <0x9>;
68		};
69	};
70
71	i2c@12CD0000 { /* i2c7 */
72		clock-frequency = <100000>;
73	       soundcodec@20 {
74	              reg = <0x20>;
75	              compatible = "maxim,max98090-codec";
76	       };
77
78		edp-lvds-bridge@48 {
79			compatible = "parade,ps8625";
80			reg = <0x48>;
81			sleep-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
82			reset-gpios = <&gpy7 7 GPIO_ACTIVE_LOW>;
83			parade,regs = /bits/ 8 <
84				0x02 0xa1 0x01  /* HPD low */
85				/*
86				* SW setting
87				* [1:0] SW output 1.2V voltage is lower to 96%
88				*/
89				0x04 0x14 0x01
90				/*
91				* RCO SS setting
92				* [5:4] = b01 0.5%, b10 1%, b11 1.5%
93				*/
94				0x04 0xe3 0x20
95				0x04 0xe2 0x80 /* [7] RCO SS enable */
96				/*
97				*  RPHY Setting
98				* [3:2] CDR tune wait cycle before
99				* measure for fine tune b00: 1us,
100				* 01: 0.5us, 10:2us, 11:4us.
101				*/
102				0x04 0x8a 0x0c
103				0x04 0x89 0x08 /* [3] RFD always on */
104				/*
105				* CTN lock in/out:
106				* 20000ppm/80000ppm. Lock out 2
107				* times.
108				*/
109				0x04 0x71 0x2d
110				/*
111				* 2.7G CDR settings
112				* NOF=40LSB for HBR CDR setting
113				*/
114				0x04 0x7d 0x07
115				0x04 0x7b 0x00  /* [1:0] Fmin=+4bands */
116				0x04 0x7a 0xfd  /* [7:5] DCO_FTRNG=+-40% */
117				/*
118				* 1.62G CDR settings
119				* [5:2]NOF=64LSB [1:0]DCO scale is 2/5
120				*/
121				0x04 0xc0 0x12
122				0x04 0xc1 0x92  /* Gitune=-37% */
123				0x04 0xc2 0x1c  /* Fbstep=100% */
124				0x04 0x32 0x80  /* [7]LOS signal disable */
125				/*
126				* RPIO Setting
127				* [7:4] LVDS driver bias current :
128				* 75% (250mV swing)
129				*/
130				0x04 0x00 0xb0
131				/*
132				* [7:6] Right-bar GPIO output strength is 8mA
133				*/
134				0x04 0x15 0x40
135				/* EQ Training State Machine Setting */
136				0x04 0x54 0x10  /* RCO calibration start */
137				/* [4:0] MAX_LANE_COUNT set to one lane */
138				0x01 0x02 0x81
139				/* [4:0] LANE_COUNT_SET set to one lane */
140				0x01 0x21 0x81
141				0x00 0x52 0x20
142				0x00 0xf1 0x03  /* HPD CP toggle enable */
143				0x00 0x62 0x41
144				/* Counter number add 1ms counter delay */
145				0x00 0xf6 0x01
146				/*
147				* [6]PWM function control by
148				* DPCD0040f[7], default is PWM
149				* block always works.
150				*/
151				0x00 0x77 0x06
152				/*
153				* 04h Adjust VTotal tolerance to
154				* fix the 30Hz no display issue
155				*/
156				0x00 0x4c 0x04
157				/* DPCD00400='h00, Parade OUI = 'h001cf8 */
158				0x01 0xc0 0x00
159				0x01 0xc1 0x1c  /* DPCD00401='h1c */
160				0x01 0xc2 0xf8  /* DPCD00402='hf8 */
161				/*
162				* DPCD403~408 = ASCII code
163				* D2SLV5='h4432534c5635
164				*/
165				0x01 0xc3 0x44
166				0x01 0xc4 0x32  /* DPCD404 */
167				0x01 0xc5 0x53  /* DPCD405 */
168				0x01 0xc6 0x4c  /* DPCD406 */
169				0x01 0xc7 0x56  /* DPCD407 */
170				0x01 0xc8 0x35  /* DPCD408 */
171				/*
172				* DPCD40A, Initial Code major  revision
173				* '01'
174				*/
175				0x01 0xca 0x01
176				/* DPCD40B Initial Code minor revision '05' */
177				0x01 0xcb 0x05
178				/* DPCD720 Select internal PWM */
179				0x01 0xa5 0xa0
180				/*
181				* FFh for 100% PWM of brightness, 0h for 0%
182				* brightness
183				*/
184				0x01 0xa7 0xff
185				/*
186				* Set LVDS output as 6bit-VESA mapping,
187				* single LVDS channel
188				*/
189				0x01 0xcc 0x13
190				/* Enable SSC set by register */
191				0x02 0xb1 0x20
192				/*
193				* Set SSC enabled and +/-1% central
194				* spreading
195				*/
196				0x04 0x10 0x16
197				/* MPU Clock source: LC => RCO */
198				0x04 0x59 0x60
199				0x04 0x54 0x14  /* LC -> RCO */
200				0x02 0xa1 0x91>;  /* HPD high */
201
202			ports {
203				port@0 {
204					bridge_out: endpoint {
205						remote-endpoint = <&panel_in>;
206					};
207				};
208
209				port@1 {
210					bridge_in: endpoint {
211						remote-endpoint = <&dp_out>;
212					};
213				};
214			};
215	        };
216	};
217
218        sound@3830000 {
219                samsung,codec-type = "max98090";
220        };
221
222	i2c@12E10000 { /* i2c9 */
223		clock-frequency = <400000>;
224		tpm@20 {
225			compatible = "infineon,slb9645tt";
226			reg = <0x20>;
227		};
228	};
229
230	panel: panel {
231		compatible = "auo,b116xw03";
232		power-supply = <&tps65090_fet6>;
233		backlight = <&backlight>;
234
235		port {
236			panel_in: endpoint {
237				remote-endpoint = <&bridge_out>;
238			};
239		};
240	};
241
242	spi@12d30000 { /* spi1 */
243		spi-max-frequency = <50000000>;
244		firmware_storage_spi: flash@0 {
245			compatible = "spi-flash";
246			reg = <0>;
247
248			/*
249			 * A region for the kernel to store a panic event
250			 * which the firmware will add to the log.
251			*/
252			elog-panic-event-offset = <0x01e00000 0x100000>;
253
254			elog-shrink-size = <0x400>;
255			elog-full-threshold = <0xc00>;
256		};
257	};
258
259	xhci@12000000 {
260		samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
261	};
262
263	xhci@12400000 {
264		samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
265	};
266
267	fimd@14400000 {
268		samsung,vl-freq = <60>;
269		samsung,vl-col = <1366>;
270		samsung,vl-row = <768>;
271		samsung,vl-width = <1366>;
272		samsung,vl-height = <768>;
273
274		samsung,vl-clkp;
275		samsung,vl-dp;
276		samsung,vl-bpix = <4>;
277
278		samsung,vl-hspw = <32>;
279		samsung,vl-hbpd = <40>;
280		samsung,vl-hfpd = <40>;
281		samsung,vl-vspw = <6>;
282		samsung,vl-vbpd = <10>;
283		samsung,vl-vfpd = <12>;
284		samsung,vl-cmd-allow-len = <0xf>;
285
286		samsung,winid = <3>;
287		samsung,interface-mode = <1>;
288		samsung,dp-enabled = <1>;
289		samsung,dual-lcd-enabled = <0>;
290	};
291};
292
293&dp {
294	status = "okay";
295	samsung,color-space = <0>;
296	samsung,dynamic-range = <0>;
297	samsung,ycbcr-coeff = <0>;
298	samsung,color-depth = <1>;
299	samsung,link-rate = <0x06>;
300	samsung,lane-count = <2>;
301	samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
302
303	ports {
304		port@0 {
305			dp_out: endpoint {
306				remote-endpoint = <&bridge_in>;
307			};
308		};
309	};
310};
311
312&spi_2 {
313	spi-max-frequency = <3125000>;
314	spi-deactivate-delay = <200>;
315	status = "okay";
316	num-cs = <1>;
317	samsung,spi-src-clk = <0>;
318	cs-gpios = <&gpb1 2 0>;
319
320	cros_ec: cros-ec@0 {
321		compatible = "google,cros-ec-spi";
322		interrupt-parent = <&gpx1>;
323		interrupts = <5 0>;
324		reg = <0>;
325		spi-half-duplex;
326		spi-max-timeout-ms = <1100>;
327		ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
328		#address-cells = <1>;
329		#size-cells = <1>;
330
331		/*
332		 * This describes the flash memory within the EC. Note
333		 * that the STM32L flash erases to 0, not 0xff.
334		 */
335		flash@8000000 {
336			reg = <0x08000000 0x20000>;
337			erase-value = <0>;
338		};
339
340		controller-data {
341			samsung,spi-feedback-delay = <1>;
342		};
343
344		i2c_tunnel: i2c-tunnel {
345			compatible = "google,cros-ec-i2c-tunnel";
346			#address-cells = <1>;
347			#size-cells = <0>;
348			google,remote-bus = <0>;
349
350			battery: sbs-battery@b {
351				compatible = "sbs,sbs-battery";
352				reg = <0xb>;
353				sbs,poll-retry-count = <1>;
354				sbs,i2c-retry-count = <2>;
355			};
356
357			power-regulator@48 {
358				compatible = "ti,tps65090";
359				reg = <0x48>;
360
361				regulators {
362					tps65090_dcdc1: dcdc1 {
363						ti,enable-ext-control;
364					};
365					tps65090_dcdc2: dcdc2 {
366						ti,enable-ext-control;
367					};
368					tps65090_dcdc3: dcdc3 {
369						ti,enable-ext-control;
370					};
371					tps65090_fet1: fet1 {
372						regulator-name = "vcd_led";
373					};
374					tps65090_fet2: fet2 {
375						regulator-name = "video_mid";
376						regulator-always-on;
377					};
378					tps65090_fet3: fet3 {
379						regulator-name = "wwan_r";
380						regulator-always-on;
381					};
382					tps65090_fet4: fet4 {
383						regulator-name = "sdcard";
384						regulator-always-on;
385					};
386					tps65090_fet5: fet5 {
387						regulator-name = "camout";
388						regulator-always-on;
389					};
390					tps65090_fet6: fet6 {
391						regulator-name = "lcd_vdd";
392					};
393					tps65090_fet7: fet7 {
394						regulator-name = "video_mid_1a";
395						regulator-always-on;
396					};
397					tps65090_ldo1: ldo1 {
398					};
399					tps65090_ldo2: ldo2 {
400					};
401				};
402
403				charger {
404					compatible = "ti,tps65090-charger";
405				};
406			};
407		};
408	};
409};
410
411#include "cros-ec-keyboard.dtsi"
412