1/* 2 * SAMSUNG/GOOGLE Peach-Pit board device tree source 3 * 4 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/dts-v1/; 11#include "exynos54xx.dtsi" 12 13/ { 14 model = "Samsung/Google Peach Pit board based on Exynos5420"; 15 16 compatible = "google,pit-rev#", "google,pit", 17 "google,peach", "samsung,exynos5420", "samsung,exynos5"; 18 19 config { 20 google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */ 21 hwid = "PIT TEST A-A 7848"; 22 lazy-init = <1>; 23 }; 24 25 aliases { 26 serial0 = "/serial@12C30000"; 27 console = "/serial@12C30000"; 28 pmic = "/i2c@12ca0000"; 29 }; 30 31 cros-ec-keyb { 32 compatible = "google,cros-ec-keyb"; 33 google,key-rows = <8>; 34 google,key-columns = <13>; 35 google,repeat-delay-ms = <240>; 36 google,repeat-rate-ms = <30>; 37 google,ghost-filter; 38 /* 39 * Keymap entries take the form of 0xRRCCKKKK where 40 * RR=Row CC=Column KKKK=Key Code 41 * The values below are for a US keyboard layout and 42 * are taken from the Linux driver. Note that the 43 * 102ND key is not used for US keyboards. 44 */ 45 linux,keymap = < 46 /* CAPSLCK F1 B F10 */ 47 0x0001003a 0x0002003b 0x00030030 0x00040044 48 /* N = R_ALT ESC */ 49 0x00060031 0x0008000d 0x000a0064 0x01010001 50 /* F4 G F7 H */ 51 0x0102003e 0x01030022 0x01040041 0x01060023 52 /* ' F9 BKSPACE L_CTRL */ 53 0x01080028 0x01090043 0x010b000e 0x0200001d 54 /* TAB F3 T F6 */ 55 0x0201000f 0x0202003d 0x02030014 0x02040040 56 /* ] Y 102ND [ */ 57 0x0205001b 0x02060015 0x02070056 0x0208001a 58 /* F8 GRAVE F2 5 */ 59 0x02090042 0x03010029 0x0302003c 0x03030006 60 /* F5 6 - \ */ 61 0x0304003f 0x03060007 0x0308000c 0x030b002b 62 /* R_CTRL A D F */ 63 0x04000061 0x0401001e 0x04020020 0x04030021 64 /* S K J ; */ 65 0x0404001f 0x04050025 0x04060024 0x04080027 66 /* L ENTER Z C */ 67 0x04090026 0x040b001c 0x0501002c 0x0502002e 68 /* V X , M */ 69 0x0503002f 0x0504002d 0x05050033 0x05060032 70 /* L_SHIFT / . SPACE */ 71 0x0507002a 0x05080035 0x05090034 0x050B0039 72 /* 1 3 4 2 */ 73 0x06010002 0x06020004 0x06030005 0x06040003 74 /* 8 7 0 9 */ 75 0x06050009 0x06060008 0x0608000b 0x0609000a 76 /* L_ALT DOWN RIGHT Q */ 77 0x060a0038 0x060b006c 0x060c006a 0x07010010 78 /* E R W I */ 79 0x07020012 0x07030013 0x07040011 0x07050017 80 /* U R_SHIFT P O */ 81 0x07060016 0x07070036 0x07080019 0x07090018 82 /* UP LEFT */ 83 0x070b0067 0x070c0069>; 84 }; 85 86 dmc { 87 mem-manuf = "samsung"; 88 mem-type = "ddr3"; 89 clock-frequency = <800000000>; 90 arm-frequency = <900000000>; 91 }; 92 93 tmu@10060000 { 94 samsung,min-temp = <25>; 95 samsung,max-temp = <125>; 96 samsung,start-warning = <95>; 97 samsung,start-tripping = <105>; 98 samsung,hw-tripping = <110>; 99 samsung,efuse-min-value = <40>; 100 samsung,efuse-value = <55>; 101 samsung,efuse-max-value = <100>; 102 samsung,slope = <274761730>; 103 samsung,dc-value = <25>; 104 }; 105 106 /* MAX77802 is on i2c bus 4 */ 107 i2c@12ca0000 { 108 clock-frequency = <400000>; 109 power-regulator@9 { 110 compatible = "maxim,max77802-pmic"; 111 reg = <0x9>; 112 }; 113 }; 114 115 i2c@12cd0000 { /* i2c7 */ 116 clock-frequency = <100000>; 117 soundcodec@20 { 118 reg = <0x20>; 119 compatible = "maxim,max98090-codec"; 120 }; 121 122 edp-lvds-bridge@48 { 123 compatible = "parade,ps8625"; 124 reg = <0x48>; 125 }; 126 }; 127 128 sound@3830000 { 129 samsung,codec-type = "max98090"; 130 }; 131 132 i2c@12e10000 { /* i2c9 */ 133 clock-frequency = <400000>; 134 tpm@20 { 135 compatible = "infineon,slb9645-tpm"; 136 reg = <0x20>; 137 }; 138 }; 139 140 spi@12d30000 { /* spi1 */ 141 spi-max-frequency = <50000000>; 142 firmware_storage_spi: flash@0 { 143 compatible = "spi-flash"; 144 reg = <0>; 145 146 /* 147 * A region for the kernel to store a panic event 148 * which the firmware will add to the log. 149 */ 150 elog-panic-event-offset = <0x01e00000 0x100000>; 151 152 elog-shrink-size = <0x400>; 153 elog-full-threshold = <0xc00>; 154 }; 155 }; 156 157 spi@12d40000 { /* spi2 */ 158 spi-max-frequency = <4000000>; 159 spi-deactivate-delay = <200>; 160 cros-ec@0 { 161 reg = <0>; 162 compatible = "google,cros-ec"; 163 spi-half-duplex; 164 spi-max-timeout-ms = <1100>; 165 spi-frame-header = <0xec>; 166 ec-interrupt = <&gpio 93 1>; /* GPX1_5 */ 167 168 /* 169 * This describes the flash memory within the EC. Note 170 * that the STM32L flash erases to 0, not 0xff. 171 */ 172 #address-cells = <1>; 173 #size-cells = <1>; 174 flash@8000000 { 175 reg = <0x08000000 0x20000>; 176 erase-value = <0>; 177 }; 178 }; 179 }; 180 181 xhci@12000000 { 182 samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */ 183 }; 184 185 xhci@12400000 { 186 samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */ 187 }; 188 189 fimd@14400000 { 190 samsung,vl-freq = <60>; 191 samsung,vl-col = <1366>; 192 samsung,vl-row = <768>; 193 samsung,vl-width = <1366>; 194 samsung,vl-height = <768>; 195 196 samsung,vl-clkp; 197 samsung,vl-dp; 198 samsung,vl-bpix = <4>; 199 200 samsung,vl-hspw = <32>; 201 samsung,vl-hbpd = <40>; 202 samsung,vl-hfpd = <40>; 203 samsung,vl-vspw = <6>; 204 samsung,vl-vbpd = <10>; 205 samsung,vl-vfpd = <12>; 206 samsung,vl-cmd-allow-len = <0xf>; 207 208 samsung,winid = <3>; 209 samsung,interface-mode = <1>; 210 samsung,dp-enabled = <1>; 211 samsung,dual-lcd-enabled = <0>; 212 }; 213}; 214