1/* 2 * Samsung's Exynos4210 SoC device tree source 3 * 4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * Copyright (c) 2010-2011 Linaro Ltd. 7 * www.linaro.org 8 * 9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 10 * based board files can include this file and provide values for board specfic 11 * bindings. 12 * 13 * Note: This file does not include device nodes for all the controllers in 14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional 15 * nodes can be added to this file. 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20*/ 21 22#include "exynos4.dtsi" 23#include "exynos4210-pinctrl.dtsi" 24 25/ { 26 compatible = "samsung,exynos4210"; 27 28 aliases { 29 pinctrl0 = &pinctrl_0; 30 pinctrl1 = &pinctrl_1; 31 pinctrl2 = &pinctrl_2; 32 }; 33 34 pd_lcd1: lcd1-power-domain@10023CA0 { 35 compatible = "samsung,exynos4210-pd"; 36 reg = <0x10023CA0 0x20>; 37 }; 38 39 gic: interrupt-controller@10490000 { 40 cpu-offset = <0x8000>; 41 }; 42 43 combiner: interrupt-controller@10440000 { 44 samsung,combiner-nr = <16>; 45 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, 46 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, 47 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, 48 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; 49 }; 50 51 mct@10050000 { 52 compatible = "samsung,exynos4210-mct"; 53 reg = <0x10050000 0x800>; 54 interrupt-parent = <&mct_map>; 55 interrupts = <0>, <1>, <2>, <3>, <4>, <5>; 56 clocks = <&clock 3>, <&clock 344>; 57 clock-names = "fin_pll", "mct"; 58 59 mct_map: mct-map { 60 #interrupt-cells = <1>; 61 #address-cells = <0>; 62 #size-cells = <0>; 63 interrupt-map = <0 &gic 0 57 0>, 64 <1 &gic 0 69 0>, 65 <2 &combiner 12 6>, 66 <3 &combiner 12 7>, 67 <4 &gic 0 42 0>, 68 <5 &gic 0 48 0>; 69 }; 70 }; 71 72 clock: clock-controller@10030000 { 73 compatible = "samsung,exynos4210-clock"; 74 reg = <0x10030000 0x20000>; 75 #clock-cells = <1>; 76 }; 77 78 pmu { 79 compatible = "arm,cortex-a9-pmu"; 80 interrupt-parent = <&combiner>; 81 interrupts = <2 2>, <3 2>; 82 }; 83 84 pinctrl_0: pinctrl@11400000 { 85 compatible = "samsung,exynos4210-pinctrl"; 86 reg = <0x11400000 0x1000>; 87 interrupts = <0 47 0>; 88 }; 89 90 pinctrl_1: pinctrl@11000000 { 91 compatible = "samsung,exynos4210-pinctrl"; 92 reg = <0x11000000 0x1000>; 93 interrupts = <0 46 0>; 94 95 wakup_eint: wakeup-interrupt-controller { 96 compatible = "samsung,exynos4210-wakeup-eint"; 97 interrupt-parent = <&gic>; 98 interrupts = <0 32 0>; 99 }; 100 }; 101 102 pinctrl_2: pinctrl@03860000 { 103 compatible = "samsung,exynos4210-pinctrl"; 104 reg = <0x03860000 0x1000>; 105 }; 106 107 tmu@100C0000 { 108 compatible = "samsung,exynos4210-tmu"; 109 interrupt-parent = <&combiner>; 110 reg = <0x100C0000 0x100>; 111 interrupts = <2 4>; 112 clocks = <&clock 383>; 113 clock-names = "tmu_apbif"; 114 status = "disabled"; 115 }; 116 117 g2d@12800000 { 118 compatible = "samsung,s5pv210-g2d"; 119 reg = <0x12800000 0x1000>; 120 interrupts = <0 89 0>; 121 clocks = <&clock 177>, <&clock 277>; 122 clock-names = "sclk_fimg2d", "fimg2d"; 123 status = "disabled"; 124 }; 125 126 camera { 127 clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; 128 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 129 130 fimc_0: fimc@11800000 { 131 samsung,pix-limits = <4224 8192 1920 4224>; 132 samsung,mainscaler-ext; 133 samsung,cam-if; 134 }; 135 136 fimc_1: fimc@11810000 { 137 samsung,pix-limits = <4224 8192 1920 4224>; 138 samsung,mainscaler-ext; 139 samsung,cam-if; 140 }; 141 142 fimc_2: fimc@11820000 { 143 samsung,pix-limits = <4224 8192 1920 4224>; 144 samsung,mainscaler-ext; 145 samsung,lcd-wb; 146 }; 147 148 fimc_3: fimc@11830000 { 149 samsung,pix-limits = <1920 8192 1366 1920>; 150 samsung,rotators = <0>; 151 samsung,mainscaler-ext; 152 samsung,lcd-wb; 153 }; 154 }; 155}; 156