1/* 2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10#include "dra72x.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 model = "TI DRA722"; 15 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; 16 17 chosen { 18 stdout-path = &uart1; 19 }; 20 21 memory { 22 device_type = "memory"; 23 reg = <0x80000000 0x40000000>; /* 1024 MB */ 24 }; 25 26 aliases { 27 display0 = &hdmi0; 28 }; 29 30 evm_3v3: fixedregulator-evm_3v3 { 31 compatible = "regulator-fixed"; 32 regulator-name = "evm_3v3"; 33 regulator-min-microvolt = <3300000>; 34 regulator-max-microvolt = <3300000>; 35 }; 36 37 extcon_usb1: extcon_usb1 { 38 compatible = "linux,extcon-usb-gpio"; 39 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 40 }; 41 42 extcon_usb2: extcon_usb2 { 43 compatible = "linux,extcon-usb-gpio"; 44 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 45 }; 46 47 hdmi0: connector { 48 compatible = "hdmi-connector"; 49 label = "hdmi"; 50 51 type = "a"; 52 53 port { 54 hdmi_connector_in: endpoint { 55 remote-endpoint = <&tpd12s015_out>; 56 }; 57 }; 58 }; 59 60 tpd12s015: encoder { 61 compatible = "ti,tpd12s015"; 62 63 pinctrl-names = "default"; 64 pinctrl-0 = <&tpd12s015_pins>; 65 66 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ 67 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ 68 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ 69 70 ports { 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 port@0 { 75 reg = <0>; 76 77 tpd12s015_in: endpoint { 78 remote-endpoint = <&hdmi_out>; 79 }; 80 }; 81 82 port@1 { 83 reg = <1>; 84 85 tpd12s015_out: endpoint { 86 remote-endpoint = <&hdmi_connector_in>; 87 }; 88 }; 89 }; 90 }; 91}; 92 93&dra7_pmx_core { 94 i2c1_pins: pinmux_i2c1_pins { 95 pinctrl-single,pins = < 96 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ 97 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ 98 >; 99 }; 100 101 i2c5_pins: pinmux_i2c5_pins { 102 pinctrl-single,pins = < 103 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ 104 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ 105 >; 106 }; 107 108 nand_default: nand_default { 109 pinctrl-single,pins = < 110 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ 111 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ 112 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ 113 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ 114 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ 115 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ 116 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ 117 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ 118 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ 119 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ 120 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ 121 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ 122 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ 123 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ 124 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ 125 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ 126 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ 127 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ 128 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ 129 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ 130 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ 131 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ 132 >; 133 }; 134 135 usb1_pins: pinmux_usb1_pins { 136 pinctrl-single,pins = < 137 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ 138 >; 139 }; 140 141 usb2_pins: pinmux_usb2_pins { 142 pinctrl-single,pins = < 143 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ 144 >; 145 }; 146 147 tps65917_pins_default: tps65917_pins_default { 148 pinctrl-single,pins = < 149 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ 150 >; 151 }; 152 153 mmc1_pins_default: mmc1_pins_default { 154 pinctrl-single,pins = < 155 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ 156 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 157 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 158 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 159 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 160 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 161 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 162 >; 163 }; 164 165 mmc2_pins_default: mmc2_pins_default { 166 pinctrl-single,pins = < 167 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 168 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 169 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 170 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 171 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 172 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 173 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 174 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 175 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 176 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 177 >; 178 }; 179 180 dcan1_pins_default: dcan1_pins_default { 181 pinctrl-single,pins = < 182 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 183 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 184 >; 185 }; 186 187 dcan1_pins_sleep: dcan1_pins_sleep { 188 pinctrl-single,pins = < 189 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 190 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ 191 >; 192 }; 193 194 qspi1_pins: pinmux_qspi1_pins { 195 pinctrl-single,pins = < 196 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ 197 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ 198 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ 199 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ 200 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ 201 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ 202 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ 203 >; 204 }; 205 206 hdmi_pins: pinmux_hdmi_pins { 207 pinctrl-single,pins = < 208 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ 209 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ 210 >; 211 }; 212 213 tpd12s015_pins: pinmux_tpd12s015_pins { 214 pinctrl-single,pins = < 215 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ 216 >; 217 }; 218}; 219 220&i2c1 { 221 status = "okay"; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&i2c1_pins>; 224 clock-frequency = <400000>; 225 226 tps65917: tps65917@58 { 227 compatible = "ti,tps65917"; 228 reg = <0x58>; 229 230 pinctrl-names = "default"; 231 pinctrl-0 = <&tps65917_pins_default>; 232 233 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ 234 interrupt-controller; 235 #interrupt-cells = <2>; 236 237 ti,system-power-controller; 238 239 tps65917_pmic { 240 compatible = "ti,tps65917-pmic"; 241 242 regulators { 243 smps1_reg: smps1 { 244 /* VDD_MPU */ 245 regulator-name = "smps1"; 246 regulator-min-microvolt = <850000>; 247 regulator-max-microvolt = <1250000>; 248 regulator-always-on; 249 regulator-boot-on; 250 }; 251 252 smps2_reg: smps2 { 253 /* VDD_CORE */ 254 regulator-name = "smps2"; 255 regulator-min-microvolt = <850000>; 256 regulator-max-microvolt = <1060000>; 257 regulator-boot-on; 258 regulator-always-on; 259 }; 260 261 smps3_reg: smps3 { 262 /* VDD_GPU IVA DSPEVE */ 263 regulator-name = "smps3"; 264 regulator-min-microvolt = <850000>; 265 regulator-max-microvolt = <1250000>; 266 regulator-boot-on; 267 regulator-always-on; 268 }; 269 270 smps4_reg: smps4 { 271 /* VDDS1V8 */ 272 regulator-name = "smps4"; 273 regulator-min-microvolt = <1800000>; 274 regulator-max-microvolt = <1800000>; 275 regulator-always-on; 276 regulator-boot-on; 277 }; 278 279 smps5_reg: smps5 { 280 /* VDD_DDR */ 281 regulator-name = "smps5"; 282 regulator-min-microvolt = <1350000>; 283 regulator-max-microvolt = <1350000>; 284 regulator-boot-on; 285 regulator-always-on; 286 }; 287 288 ldo1_reg: ldo1 { 289 /* LDO1_OUT --> SDIO */ 290 regulator-name = "ldo1"; 291 regulator-min-microvolt = <1800000>; 292 regulator-max-microvolt = <3300000>; 293 regulator-boot-on; 294 }; 295 296 ldo2_reg: ldo2 { 297 /* LDO2_OUT --> TP1017 (UNUSED) */ 298 regulator-name = "ldo2"; 299 regulator-min-microvolt = <1800000>; 300 regulator-max-microvolt = <3300000>; 301 }; 302 303 ldo3_reg: ldo3 { 304 /* VDDA_1V8_PHY */ 305 regulator-name = "ldo3"; 306 regulator-min-microvolt = <1800000>; 307 regulator-max-microvolt = <1800000>; 308 regulator-boot-on; 309 regulator-always-on; 310 }; 311 312 ldo5_reg: ldo5 { 313 /* VDDA_1V8_PLL */ 314 regulator-name = "ldo5"; 315 regulator-min-microvolt = <1800000>; 316 regulator-max-microvolt = <1800000>; 317 regulator-always-on; 318 regulator-boot-on; 319 }; 320 321 ldo4_reg: ldo4 { 322 /* VDDA_3V_USB: VDDA_USBHS33 */ 323 regulator-name = "ldo4"; 324 regulator-min-microvolt = <3300000>; 325 regulator-max-microvolt = <3300000>; 326 regulator-boot-on; 327 }; 328 }; 329 }; 330 331 tps65917_power_button { 332 compatible = "ti,palmas-pwrbutton"; 333 interrupt-parent = <&tps65917>; 334 interrupts = <1 IRQ_TYPE_NONE>; 335 wakeup-source; 336 ti,palmas-long-press-seconds = <6>; 337 }; 338 }; 339 340 pcf_gpio_21: gpio@21 { 341 compatible = "ti,pcf8575"; 342 reg = <0x21>; 343 lines-initial-states = <0x1408>; 344 gpio-controller; 345 #gpio-cells = <2>; 346 interrupt-parent = <&gpio6>; 347 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 }; 351}; 352 353&i2c5 { 354 status = "okay"; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&i2c5_pins>; 357 clock-frequency = <400000>; 358 359 pcf_hdmi: pcf8575@26 { 360 compatible = "nxp,pcf8575"; 361 reg = <0x26>; 362 gpio-controller; 363 #gpio-cells = <2>; 364 /* 365 * initial state is used here to keep the mdio interface 366 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and 367 * VIN2_S0 driven high otherwise Ethernet stops working 368 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 369 */ 370 lines-initial-states = <0x0f2b>; 371 }; 372}; 373 374&uart1 { 375 status = "okay"; 376}; 377 378&elm { 379 status = "okay"; 380}; 381 382&gpmc { 383 status = "okay"; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&nand_default>; 386 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 387 nand@0,0 { 388 /* To use NAND, DIP switch SW5 must be set like so: 389 * SW5.1 (NAND_SELn) = ON (LOW) 390 * SW5.9 (GPMC_WPN) = OFF (HIGH) 391 */ 392 reg = <0 0 4>; /* device IO registers */ 393 ti,nand-ecc-opt = "bch8"; 394 ti,elm-id = <&elm>; 395 nand-bus-width = <16>; 396 gpmc,device-width = <2>; 397 gpmc,sync-clk-ps = <0>; 398 gpmc,cs-on-ns = <0>; 399 gpmc,cs-rd-off-ns = <80>; 400 gpmc,cs-wr-off-ns = <80>; 401 gpmc,adv-on-ns = <0>; 402 gpmc,adv-rd-off-ns = <60>; 403 gpmc,adv-wr-off-ns = <60>; 404 gpmc,we-on-ns = <10>; 405 gpmc,we-off-ns = <50>; 406 gpmc,oe-on-ns = <4>; 407 gpmc,oe-off-ns = <40>; 408 gpmc,access-ns = <40>; 409 gpmc,wr-access-ns = <80>; 410 gpmc,rd-cycle-ns = <80>; 411 gpmc,wr-cycle-ns = <80>; 412 gpmc,bus-turnaround-ns = <0>; 413 gpmc,cycle2cycle-delay-ns = <0>; 414 gpmc,clk-activation-ns = <0>; 415 gpmc,wait-monitoring-ns = <0>; 416 gpmc,wr-data-mux-bus-ns = <0>; 417 /* MTD partition table */ 418 /* All SPL-* partitions are sized to minimal length 419 * which can be independently programmable. For 420 * NAND flash this is equal to size of erase-block */ 421 #address-cells = <1>; 422 #size-cells = <1>; 423 partition@0 { 424 label = "NAND.SPL"; 425 reg = <0x00000000 0x000020000>; 426 }; 427 partition@1 { 428 label = "NAND.SPL.backup1"; 429 reg = <0x00020000 0x00020000>; 430 }; 431 partition@2 { 432 label = "NAND.SPL.backup2"; 433 reg = <0x00040000 0x00020000>; 434 }; 435 partition@3 { 436 label = "NAND.SPL.backup3"; 437 reg = <0x00060000 0x00020000>; 438 }; 439 partition@4 { 440 label = "NAND.u-boot-spl-os"; 441 reg = <0x00080000 0x00040000>; 442 }; 443 partition@5 { 444 label = "NAND.u-boot"; 445 reg = <0x000c0000 0x00100000>; 446 }; 447 partition@6 { 448 label = "NAND.u-boot-env"; 449 reg = <0x001c0000 0x00020000>; 450 }; 451 partition@7 { 452 label = "NAND.u-boot-env.backup1"; 453 reg = <0x001e0000 0x00020000>; 454 }; 455 partition@8 { 456 label = "NAND.kernel"; 457 reg = <0x00200000 0x00800000>; 458 }; 459 partition@9 { 460 label = "NAND.file-system"; 461 reg = <0x00a00000 0x0f600000>; 462 }; 463 }; 464}; 465 466&usb2_phy1 { 467 phy-supply = <&ldo4_reg>; 468}; 469 470&usb2_phy2 { 471 phy-supply = <&ldo4_reg>; 472}; 473 474&omap_dwc3_1 { 475 extcon = <&extcon_usb1>; 476}; 477 478&omap_dwc3_2 { 479 extcon = <&extcon_usb2>; 480}; 481 482&usb1 { 483 dr_mode = "peripheral"; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&usb1_pins>; 486}; 487 488&usb2 { 489 dr_mode = "host"; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&usb2_pins>; 492}; 493 494&mmc1 { 495 status = "okay"; 496 pinctrl-names = "default"; 497 pinctrl-0 = <&mmc1_pins_default>; 498 499 vmmc-supply = <&ldo1_reg>; 500 bus-width = <4>; 501 /* 502 * SDCD signal is not being used here - using the fact that GPIO mode 503 * is a viable alternative 504 */ 505 cd-gpios = <&gpio6 27 0>; 506}; 507 508&mmc2 { 509 /* SW5-3 in ON position */ 510 status = "okay"; 511 pinctrl-names = "default"; 512 pinctrl-0 = <&mmc2_pins_default>; 513 514 vmmc-supply = <&evm_3v3>; 515 bus-width = <8>; 516 ti,non-removable; 517}; 518 519&dra7_pmx_core { 520 cpsw_default: cpsw_default { 521 pinctrl-single,pins = < 522 /* Slave 2 */ 523 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ 524 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ 525 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ 526 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ 527 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ 528 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ 529 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ 530 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ 531 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ 532 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ 533 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ 534 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ 535 >; 536 537 }; 538 539 cpsw_sleep: cpsw_sleep { 540 pinctrl-single,pins = < 541 /* Slave 2 */ 542 0x198 (MUX_MODE15) 543 0x19c (MUX_MODE15) 544 0x1a0 (MUX_MODE15) 545 0x1a4 (MUX_MODE15) 546 0x1a8 (MUX_MODE15) 547 0x1ac (MUX_MODE15) 548 0x1b0 (MUX_MODE15) 549 0x1b4 (MUX_MODE15) 550 0x1b8 (MUX_MODE15) 551 0x1bc (MUX_MODE15) 552 0x1c0 (MUX_MODE15) 553 0x1c4 (MUX_MODE15) 554 >; 555 }; 556 557 davinci_mdio_default: davinci_mdio_default { 558 pinctrl-single,pins = < 559 /* MDIO */ 560 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ 561 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 562 >; 563 }; 564 565 davinci_mdio_sleep: davinci_mdio_sleep { 566 pinctrl-single,pins = < 567 0x23c (MUX_MODE15) 568 0x240 (MUX_MODE15) 569 >; 570 }; 571}; 572 573&mac { 574 status = "okay"; 575 pinctrl-names = "default", "sleep"; 576 pinctrl-0 = <&cpsw_default>; 577 pinctrl-1 = <&cpsw_sleep>; 578}; 579 580&cpsw_emac1 { 581 phy_id = <&davinci_mdio>, <3>; 582 phy-mode = "rgmii"; 583}; 584 585&davinci_mdio { 586 pinctrl-names = "default", "sleep"; 587 pinctrl-0 = <&davinci_mdio_default>; 588 pinctrl-1 = <&davinci_mdio_sleep>; 589 active_slave = <1>; 590}; 591 592&dcan1 { 593 status = "ok"; 594 pinctrl-names = "default", "sleep", "active"; 595 pinctrl-0 = <&dcan1_pins_sleep>; 596 pinctrl-1 = <&dcan1_pins_sleep>; 597 pinctrl-2 = <&dcan1_pins_default>; 598}; 599 600&qspi { 601 status = "okay"; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&qspi1_pins>; 604 605 spi-max-frequency = <48000000>; 606 m25p80@0 { 607 compatible = "s25fl256s1"; 608 spi-max-frequency = <48000000>; 609 reg = <0>; 610 spi-tx-bus-width = <1>; 611 spi-rx-bus-width = <4>; 612 spi-cpol; 613 spi-cpha; 614 #address-cells = <1>; 615 #size-cells = <1>; 616 617 /* MTD partition table. 618 * The ROM checks the first four physical blocks 619 * for a valid file to boot and the flash here is 620 * 64KiB block size. 621 */ 622 partition@0 { 623 label = "QSPI.SPL"; 624 reg = <0x00000000 0x000010000>; 625 }; 626 partition@1 { 627 label = "QSPI.SPL.backup1"; 628 reg = <0x00010000 0x00010000>; 629 }; 630 partition@2 { 631 label = "QSPI.SPL.backup2"; 632 reg = <0x00020000 0x00010000>; 633 }; 634 partition@3 { 635 label = "QSPI.SPL.backup3"; 636 reg = <0x00030000 0x00010000>; 637 }; 638 partition@4 { 639 label = "QSPI.u-boot"; 640 reg = <0x00040000 0x00100000>; 641 }; 642 partition@5 { 643 label = "QSPI.u-boot-spl-os"; 644 reg = <0x00140000 0x00080000>; 645 }; 646 partition@6 { 647 label = "QSPI.u-boot-env"; 648 reg = <0x001c0000 0x00010000>; 649 }; 650 partition@7 { 651 label = "QSPI.u-boot-env.backup1"; 652 reg = <0x001d0000 0x0010000>; 653 }; 654 partition@8 { 655 label = "QSPI.kernel"; 656 reg = <0x001e0000 0x0800000>; 657 }; 658 partition@9 { 659 label = "QSPI.file-system"; 660 reg = <0x009e0000 0x01620000>; 661 }; 662 }; 663}; 664 665&dss { 666 status = "ok"; 667 668 vdda_video-supply = <&ldo5_reg>; 669}; 670 671&hdmi { 672 status = "ok"; 673 vdda-supply = <&ldo3_reg>; 674 675 pinctrl-names = "default"; 676 pinctrl-0 = <&hdmi_pins>; 677 678 port { 679 hdmi_out: endpoint { 680 remote-endpoint = <&tpd12s015_in>; 681 }; 682 }; 683}; 684