1/* 2 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10#include "dra72x.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/clk/ti-dra7-atl.h> 13 14/ { 15 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; 16 17 aliases { 18 display0 = &hdmi0; 19 }; 20 21 chosen { 22 stdout-path = &uart1; 23 tick-timer = &timer2; 24 }; 25 26 evm_12v0: fixedregulator-evm12v0 { 27 /* main supply */ 28 compatible = "regulator-fixed"; 29 regulator-name = "evm_12v0"; 30 regulator-min-microvolt = <12000000>; 31 regulator-max-microvolt = <12000000>; 32 regulator-always-on; 33 regulator-boot-on; 34 }; 35 36 evm_5v0: fixedregulator-evm5v0 { 37 /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */ 38 /* Output 1 of LM5140QRWGTQ1 on dra71-evm */ 39 compatible = "regulator-fixed"; 40 regulator-name = "evm_5v0"; 41 regulator-min-microvolt = <5000000>; 42 regulator-max-microvolt = <5000000>; 43 vin-supply = <&evm_12v0>; 44 regulator-always-on; 45 regulator-boot-on; 46 }; 47 48 vsys_3v3: fixedregulator-vsys3v3 { 49 /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */ 50 /* Output 2 of LM5140QRWGTQ1 on dra71-evm */ 51 compatible = "regulator-fixed"; 52 regulator-name = "vsys_3v3"; 53 regulator-min-microvolt = <3300000>; 54 regulator-max-microvolt = <3300000>; 55 vin-supply = <&evm_12v0>; 56 regulator-always-on; 57 regulator-boot-on; 58 }; 59 60 evm_3v3_sw: fixedregulator-evm_3v3 { 61 /* TPS22965DSG */ 62 compatible = "regulator-fixed"; 63 regulator-name = "evm_3v3"; 64 regulator-min-microvolt = <3300000>; 65 regulator-max-microvolt = <3300000>; 66 vin-supply = <&vsys_3v3>; 67 regulator-always-on; 68 regulator-boot-on; 69 }; 70 71 aic_dvdd: fixedregulator-aic_dvdd { 72 /* TPS77018DBVT */ 73 compatible = "regulator-fixed"; 74 regulator-name = "aic_dvdd"; 75 vin-supply = <&evm_3v3_sw>; 76 regulator-min-microvolt = <1800000>; 77 regulator-max-microvolt = <1800000>; 78 }; 79 80 evm_3v3_sd: fixedregulator-sd { 81 compatible = "regulator-fixed"; 82 regulator-name = "evm_3v3_sd"; 83 regulator-min-microvolt = <3300000>; 84 regulator-max-microvolt = <3300000>; 85 vin-supply = <&evm_3v3_sw>; 86 enable-active-high; 87 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; 88 }; 89 90 extcon_usb1: extcon_usb1 { 91 compatible = "linux,extcon-usb-gpio"; 92 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 93 }; 94 95 extcon_usb2: extcon_usb2 { 96 compatible = "linux,extcon-usb-gpio"; 97 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 98 }; 99 100 hdmi0: connector { 101 compatible = "hdmi-connector"; 102 label = "hdmi"; 103 104 type = "a"; 105 106 port { 107 hdmi_connector_in: endpoint { 108 remote-endpoint = <&tpd12s015_out>; 109 }; 110 }; 111 }; 112 113 tpd12s015: encoder { 114 compatible = "ti,tpd12s015"; 115 116 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ 117 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ 118 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ 119 120 ports { 121 #address-cells = <1>; 122 #size-cells = <0>; 123 124 port@0 { 125 reg = <0>; 126 127 tpd12s015_in: endpoint { 128 remote-endpoint = <&hdmi_out>; 129 }; 130 }; 131 132 port@1 { 133 reg = <1>; 134 135 tpd12s015_out: endpoint { 136 remote-endpoint = <&hdmi_connector_in>; 137 }; 138 }; 139 }; 140 }; 141 142 sound0: sound0 { 143 compatible = "simple-audio-card"; 144 simple-audio-card,name = "DRA7xx-EVM"; 145 simple-audio-card,widgets = 146 "Headphone", "Headphone Jack", 147 "Line", "Line Out", 148 "Microphone", "Mic Jack", 149 "Line", "Line In"; 150 simple-audio-card,routing = 151 "Headphone Jack", "HPLOUT", 152 "Headphone Jack", "HPROUT", 153 "Line Out", "LLOUT", 154 "Line Out", "RLOUT", 155 "MIC3L", "Mic Jack", 156 "MIC3R", "Mic Jack", 157 "Mic Jack", "Mic Bias", 158 "LINE1L", "Line In", 159 "LINE1R", "Line In"; 160 simple-audio-card,format = "dsp_b"; 161 simple-audio-card,bitclock-master = <&sound0_master>; 162 simple-audio-card,frame-master = <&sound0_master>; 163 simple-audio-card,bitclock-inversion; 164 165 sound0_master: simple-audio-card,cpu { 166 sound-dai = <&mcasp3>; 167 system-clock-frequency = <5644800>; 168 }; 169 170 simple-audio-card,codec { 171 sound-dai = <&tlv320aic3106>; 172 clocks = <&atl_clkin2_ck>; 173 }; 174 }; 175}; 176 177&dra7_pmx_core { 178 mmc1_pins_default: mmc1_pins_default { 179 pinctrl-single,pins = < 180 DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ 181 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 182 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 183 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 184 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 185 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 186 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 187 >; 188 }; 189 190 mmc2_pins_default: mmc2_pins_default { 191 pinctrl-single,pins = < 192 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 193 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 194 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 195 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 196 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 197 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 198 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 199 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 200 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 201 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 202 >; 203 }; 204 205 dcan1_pins_default: dcan1_pins_default { 206 pinctrl-single,pins = < 207 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 208 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 209 >; 210 }; 211 212 dcan1_pins_sleep: dcan1_pins_sleep { 213 pinctrl-single,pins = < 214 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 215 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ 216 >; 217 }; 218}; 219 220&i2c1 { 221 status = "okay"; 222 clock-frequency = <400000>; 223 224 pcf_gpio_21: gpio@21 { 225 compatible = "ti,pcf8575", "nxp,pcf8575"; 226 u-boot,i2c-offset-len = <0>; 227 reg = <0x21>; 228 lines-initial-states = <0x1408>; 229 gpio-controller; 230 #gpio-cells = <2>; 231 interrupt-controller; 232 #interrupt-cells = <2>; 233 }; 234 235 tlv320aic3106: tlv320aic3106@19 { 236 #sound-dai-cells = <0>; 237 compatible = "ti,tlv320aic3106"; 238 reg = <0x19>; 239 adc-settle-ms = <40>; 240 ai3x-micbias-vg = <1>; /* 2.0V */ 241 status = "okay"; 242 243 /* Regulators */ 244 AVDD-supply = <&evm_3v3_sw>; 245 IOVDD-supply = <&evm_3v3_sw>; 246 DRVDD-supply = <&evm_3v3_sw>; 247 DVDD-supply = <&aic_dvdd>; 248 }; 249}; 250 251&i2c5 { 252 status = "okay"; 253 clock-frequency = <400000>; 254 255 pcf_hdmi: pcf8575@26 { 256 compatible = "ti,pcf8575", "nxp,pcf8575"; 257 u-boot,i2c-offset-len = <0>; 258 reg = <0x26>; 259 gpio-controller; 260 #gpio-cells = <2>; 261 /* 262 * initial state is used here to keep the mdio interface 263 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and 264 * VIN2_S0 driven high otherwise Ethernet stops working 265 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 266 */ 267 lines-initial-states = <0x0f2b>; 268 269 p1 { 270 /* vin6_sel_s0: high: VIN6, low: audio */ 271 gpio-hog; 272 gpios = <1 GPIO_ACTIVE_HIGH>; 273 output-low; 274 line-name = "vin6_sel_s0"; 275 }; 276 }; 277}; 278 279&uart1 { 280 status = "okay"; 281 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 282 <&dra7_pmx_core 0x3e0>; 283}; 284 285&elm { 286 status = "okay"; 287}; 288 289&gpmc { 290 status = "okay"; 291 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ 292 nand@0,0 { 293 /* To use NAND, DIP switch SW5 must be set like so: 294 * SW5.1 (NAND_SELn) = ON (LOW) 295 * SW5.9 (GPMC_WPN) = OFF (HIGH) 296 */ 297 compatible = "ti,omap2-nand"; 298 reg = <0 0 4>; /* device IO registers */ 299 interrupt-parent = <&gpmc>; 300 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 301 <1 IRQ_TYPE_NONE>; /* termcount */ 302 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ 303 ti,nand-ecc-opt = "bch8"; 304 ti,elm-id = <&elm>; 305 nand-bus-width = <16>; 306 gpmc,device-width = <2>; 307 gpmc,sync-clk-ps = <0>; 308 gpmc,cs-on-ns = <0>; 309 gpmc,cs-rd-off-ns = <80>; 310 gpmc,cs-wr-off-ns = <80>; 311 gpmc,adv-on-ns = <0>; 312 gpmc,adv-rd-off-ns = <60>; 313 gpmc,adv-wr-off-ns = <60>; 314 gpmc,we-on-ns = <10>; 315 gpmc,we-off-ns = <50>; 316 gpmc,oe-on-ns = <4>; 317 gpmc,oe-off-ns = <40>; 318 gpmc,access-ns = <40>; 319 gpmc,wr-access-ns = <80>; 320 gpmc,rd-cycle-ns = <80>; 321 gpmc,wr-cycle-ns = <80>; 322 gpmc,bus-turnaround-ns = <0>; 323 gpmc,cycle2cycle-delay-ns = <0>; 324 gpmc,clk-activation-ns = <0>; 325 gpmc,wr-data-mux-bus-ns = <0>; 326 /* MTD partition table */ 327 /* All SPL-* partitions are sized to minimal length 328 * which can be independently programmable. For 329 * NAND flash this is equal to size of erase-block */ 330 #address-cells = <1>; 331 #size-cells = <1>; 332 partition@0 { 333 label = "NAND.SPL"; 334 reg = <0x00000000 0x000020000>; 335 }; 336 partition@1 { 337 label = "NAND.SPL.backup1"; 338 reg = <0x00020000 0x00020000>; 339 }; 340 partition@2 { 341 label = "NAND.SPL.backup2"; 342 reg = <0x00040000 0x00020000>; 343 }; 344 partition@3 { 345 label = "NAND.SPL.backup3"; 346 reg = <0x00060000 0x00020000>; 347 }; 348 partition@4 { 349 label = "NAND.u-boot-spl-os"; 350 reg = <0x00080000 0x00040000>; 351 }; 352 partition@5 { 353 label = "NAND.u-boot"; 354 reg = <0x000c0000 0x00100000>; 355 }; 356 partition@6 { 357 label = "NAND.u-boot-env"; 358 reg = <0x001c0000 0x00020000>; 359 }; 360 partition@7 { 361 label = "NAND.u-boot-env.backup1"; 362 reg = <0x001e0000 0x00020000>; 363 }; 364 partition@8 { 365 label = "NAND.kernel"; 366 reg = <0x00200000 0x00800000>; 367 }; 368 partition@9 { 369 label = "NAND.file-system"; 370 reg = <0x00a00000 0x0f600000>; 371 }; 372 }; 373}; 374 375&omap_dwc3_1 { 376 extcon = <&extcon_usb1>; 377}; 378 379&omap_dwc3_2 { 380 extcon = <&extcon_usb2>; 381}; 382 383&usb1 { 384 dr_mode = "peripheral"; 385}; 386 387&usb2 { 388 dr_mode = "host"; 389}; 390 391&mmc1 { 392 status = "okay"; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&mmc1_pins_default>; 395 vmmc-supply = <&evm_3v3_sd>; 396 bus-width = <4>; 397 /* 398 * SDCD signal is not being used here - using the fact that GPIO mode 399 * is a viable alternative 400 */ 401 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; 402 max-frequency = <192000000>; 403}; 404 405&mmc2 { 406 /* SW5-3 in ON position */ 407 status = "okay"; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&mmc2_pins_default>; 410 411 vmmc-supply = <&evm_3v3_sw>; 412 bus-width = <8>; 413 ti,non-removable; 414 max-frequency = <192000000>; 415}; 416 417&mac { 418 status = "okay"; 419}; 420 421&dcan1 { 422 status = "ok"; 423 pinctrl-names = "default", "sleep", "active"; 424 pinctrl-0 = <&dcan1_pins_sleep>; 425 pinctrl-1 = <&dcan1_pins_sleep>; 426 pinctrl-2 = <&dcan1_pins_default>; 427}; 428 429&qspi { 430 status = "okay"; 431 432 spi-max-frequency = <76800000>; 433 m25p80@0 { 434 compatible = "s25fl256s1", "spi-flash"; 435 spi-max-frequency = <76800000>; 436 reg = <0>; 437 spi-tx-bus-width = <1>; 438 spi-rx-bus-width = <4>; 439 #address-cells = <1>; 440 #size-cells = <1>; 441 442 /* MTD partition table. 443 * The ROM checks the first four physical blocks 444 * for a valid file to boot and the flash here is 445 * 64KiB block size. 446 */ 447 partition@0 { 448 label = "QSPI.SPL"; 449 reg = <0x00000000 0x000010000>; 450 }; 451 partition@1 { 452 label = "QSPI.SPL.backup1"; 453 reg = <0x00010000 0x00010000>; 454 }; 455 partition@2 { 456 label = "QSPI.SPL.backup2"; 457 reg = <0x00020000 0x00010000>; 458 }; 459 partition@3 { 460 label = "QSPI.SPL.backup3"; 461 reg = <0x00030000 0x00010000>; 462 }; 463 partition@4 { 464 label = "QSPI.u-boot"; 465 reg = <0x00040000 0x00100000>; 466 }; 467 partition@5 { 468 label = "QSPI.u-boot-spl-os"; 469 reg = <0x00140000 0x00080000>; 470 }; 471 partition@6 { 472 label = "QSPI.u-boot-env"; 473 reg = <0x001c0000 0x00010000>; 474 }; 475 partition@7 { 476 label = "QSPI.u-boot-env.backup1"; 477 reg = <0x001d0000 0x0010000>; 478 }; 479 partition@8 { 480 label = "QSPI.kernel"; 481 reg = <0x001e0000 0x0800000>; 482 }; 483 partition@9 { 484 label = "QSPI.file-system"; 485 reg = <0x009e0000 0x01620000>; 486 }; 487 }; 488}; 489 490&dss { 491 status = "ok"; 492}; 493 494&hdmi { 495 status = "ok"; 496 497 port { 498 hdmi_out: endpoint { 499 remote-endpoint = <&tpd12s015_in>; 500 }; 501 }; 502}; 503 504&atl { 505 assigned-clocks = <&abe_dpll_sys_clk_mux>, 506 <&atl_gfclk_mux>, 507 <&dpll_abe_ck>, 508 <&dpll_abe_m2x2_ck>, 509 <&atl_clkin2_ck>; 510 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; 511 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; 512 513 status = "okay"; 514 515 atl2 { 516 bws = <DRA7_ATL_WS_MCASP2_FSX>; 517 aws = <DRA7_ATL_WS_MCASP3_FSX>; 518 }; 519}; 520 521&mcasp3 { 522 #sound-dai-cells = <0>; 523 524 assigned-clocks = <&mcasp3_ahclkx_mux>; 525 assigned-clock-parents = <&atl_clkin2_ck>; 526 527 status = "okay"; 528 529 op-mode = <0>; /* MCASP_IIS_MODE */ 530 tdm-slots = <2>; 531 /* 4 serializer */ 532 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 533 1 2 0 0 534 >; 535 tx-num-evt = <32>; 536 rx-num-evt = <32>; 537}; 538 539&mailbox5 { 540 status = "okay"; 541 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { 542 status = "okay"; 543 }; 544 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { 545 status = "okay"; 546 }; 547}; 548 549&mailbox6 { 550 status = "okay"; 551 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { 552 status = "okay"; 553 }; 554}; 555