xref: /openbmc/u-boot/arch/arm/dts/dra7.dtsi (revision 5994e8b6)
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#define MAX_SOURCES 400
14
15/ {
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	compatible = "ti,dra7xx";
20	interrupt-parent = <&crossbar_mpu>;
21	chosen { };
22
23	aliases {
24		i2c0 = &i2c1;
25		i2c1 = &i2c2;
26		i2c2 = &i2c3;
27		i2c3 = &i2c4;
28		i2c4 = &i2c5;
29		serial0 = &uart1;
30		serial1 = &uart2;
31		serial2 = &uart3;
32		serial3 = &uart4;
33		serial4 = &uart5;
34		serial5 = &uart6;
35		serial6 = &uart7;
36		serial7 = &uart8;
37		serial8 = &uart9;
38		serial9 = &uart10;
39		ethernet0 = &cpsw_emac0;
40		ethernet1 = &cpsw_emac1;
41		d_can0 = &dcan1;
42		d_can1 = &dcan2;
43		spi0 = &qspi;
44	};
45
46	timer {
47		compatible = "arm,armv7-timer";
48		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
52		interrupt-parent = <&gic>;
53	};
54
55	gic: interrupt-controller@48211000 {
56		compatible = "arm,cortex-a15-gic";
57		interrupt-controller;
58		#interrupt-cells = <3>;
59		reg = <0x0 0x48211000 0x0 0x1000>,
60		      <0x0 0x48212000 0x0 0x2000>,
61		      <0x0 0x48214000 0x0 0x2000>,
62		      <0x0 0x48216000 0x0 0x2000>;
63		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
64		interrupt-parent = <&gic>;
65	};
66
67	wakeupgen: interrupt-controller@48281000 {
68		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
69		interrupt-controller;
70		#interrupt-cells = <3>;
71		reg = <0x0 0x48281000 0x0 0x1000>;
72		interrupt-parent = <&gic>;
73	};
74
75	cpus {
76		#address-cells = <1>;
77		#size-cells = <0>;
78
79		cpu0: cpu@0 {
80			device_type = "cpu";
81			compatible = "arm,cortex-a15";
82			reg = <0>;
83
84			operating-points-v2 = <&cpu0_opp_table>;
85
86			clocks = <&dpll_mpu_ck>;
87			clock-names = "cpu";
88
89			clock-latency = <300000>; /* From omap-cpufreq driver */
90
91			/* cooling options */
92			cooling-min-level = <0>;
93			cooling-max-level = <2>;
94			#cooling-cells = <2>; /* min followed by max */
95		};
96	};
97
98	cpu0_opp_table: opp-table {
99		compatible = "operating-points-v2-ti-cpu";
100		syscon = <&scm_wkup>;
101
102		opp_nom-1000000000 {
103			opp-hz = /bits/ 64 <1000000000>;
104			opp-microvolt = <1060000 850000 1150000>;
105			opp-supported-hw = <0xFF 0x01>;
106			opp-suspend;
107		};
108
109		opp_od-1176000000 {
110			opp-hz = /bits/ 64 <1176000000>;
111			opp-microvolt = <1160000 885000 1160000>;
112			opp-supported-hw = <0xFF 0x02>;
113		};
114	};
115
116	/*
117	 * The soc node represents the soc top level view. It is used for IPs
118	 * that are not memory mapped in the MPU view or for the MPU itself.
119	 */
120	soc {
121		compatible = "ti,omap-infra";
122		mpu {
123			compatible = "ti,omap5-mpu";
124			ti,hwmods = "mpu";
125		};
126	};
127
128	/*
129	 * XXX: Use a flat representation of the SOC interconnect.
130	 * The real OMAP interconnect network is quite complex.
131	 * Since it will not bring real advantage to represent that in DT for
132	 * the moment, just use a fake OCP bus entry to represent the whole bus
133	 * hierarchy.
134	 */
135	ocp {
136		compatible = "ti,dra7-l3-noc", "simple-bus";
137		#address-cells = <1>;
138		#size-cells = <1>;
139		ranges = <0x0 0x0 0x0 0xc0000000>;
140		ti,hwmods = "l3_main_1", "l3_main_2";
141		reg = <0x0 0x44000000 0x0 0x1000000>,
142		      <0x0 0x45000000 0x0 0x1000>;
143		interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
144				      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
145
146		l4_cfg: l4@4a000000 {
147			compatible = "ti,dra7-l4-cfg", "simple-bus";
148			#address-cells = <1>;
149			#size-cells = <1>;
150			ranges = <0 0x4a000000 0x22c000>;
151
152			scm: scm@2000 {
153				compatible = "ti,dra7-scm-core", "simple-bus";
154				reg = <0x2000 0x2000>;
155				#address-cells = <1>;
156				#size-cells = <1>;
157				ranges = <0 0x2000 0x2000>;
158
159				scm_conf: scm_conf@0 {
160					compatible = "syscon", "simple-bus";
161					reg = <0x0 0x1400>;
162					#address-cells = <1>;
163					#size-cells = <1>;
164					ranges = <0 0x0 0x1400>;
165
166					pbias_regulator: pbias_regulator@e00 {
167						compatible = "ti,pbias-dra7", "ti,pbias-omap";
168						reg = <0xe00 0x4>;
169						syscon = <&scm_conf>;
170						pbias_mmc_reg: pbias_mmc_omap5 {
171							regulator-name = "pbias_mmc_omap5";
172							regulator-min-microvolt = <1800000>;
173							regulator-max-microvolt = <3000000>;
174						};
175					};
176
177					scm_conf_clocks: clocks {
178						#address-cells = <1>;
179						#size-cells = <0>;
180					};
181				};
182
183				dra7_pmx_core: pinmux@1400 {
184					compatible = "ti,dra7-padconf",
185						     "pinctrl-single";
186					reg = <0x1400 0x0468>;
187					#address-cells = <1>;
188					#size-cells = <0>;
189					#pinctrl-cells = <1>;
190					#interrupt-cells = <1>;
191					interrupt-controller;
192					pinctrl-single,register-width = <32>;
193					pinctrl-single,function-mask = <0x3fffffff>;
194				};
195
196				scm_conf1: scm_conf@1c04 {
197					compatible = "syscon";
198					reg = <0x1c04 0x0020>;
199					#syscon-cells = <2>;
200				};
201
202				scm_conf_pcie: scm_conf@1c24 {
203					compatible = "syscon";
204					reg = <0x1c24 0x0024>;
205				};
206
207				sdma_xbar: dma-router@b78 {
208					compatible = "ti,dra7-dma-crossbar";
209					reg = <0xb78 0xfc>;
210					#dma-cells = <1>;
211					dma-requests = <205>;
212					ti,dma-safe-map = <0>;
213					dma-masters = <&sdma>;
214				};
215
216				edma_xbar: dma-router@c78 {
217					compatible = "ti,dra7-dma-crossbar";
218					reg = <0xc78 0x7c>;
219					#dma-cells = <2>;
220					dma-requests = <204>;
221					ti,dma-safe-map = <0>;
222					dma-masters = <&edma>;
223				};
224			};
225
226			cm_core_aon: cm_core_aon@5000 {
227				compatible = "ti,dra7-cm-core-aon";
228				reg = <0x5000 0x2000>;
229
230				cm_core_aon_clocks: clocks {
231					#address-cells = <1>;
232					#size-cells = <0>;
233				};
234
235				cm_core_aon_clockdomains: clockdomains {
236				};
237			};
238
239			cm_core: cm_core@8000 {
240				compatible = "ti,dra7-cm-core";
241				reg = <0x8000 0x3000>;
242
243				cm_core_clocks: clocks {
244					#address-cells = <1>;
245					#size-cells = <0>;
246				};
247
248				cm_core_clockdomains: clockdomains {
249				};
250			};
251		};
252
253		l4_wkup: l4@4ae00000 {
254			compatible = "ti,dra7-l4-wkup", "simple-bus";
255			#address-cells = <1>;
256			#size-cells = <1>;
257			ranges = <0 0x4ae00000 0x3f000>;
258
259			counter32k: counter@4000 {
260				compatible = "ti,omap-counter32k";
261				reg = <0x4000 0x40>;
262				ti,hwmods = "counter_32k";
263			};
264
265			prm: prm@6000 {
266				compatible = "ti,dra7-prm";
267				reg = <0x6000 0x3000>;
268				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
269
270				prm_clocks: clocks {
271					#address-cells = <1>;
272					#size-cells = <0>;
273				};
274
275				prm_clockdomains: clockdomains {
276				};
277			};
278
279			scm_wkup: scm_conf@c000 {
280				compatible = "syscon";
281				reg = <0xc000 0x1000>;
282			};
283		};
284
285		axi@0 {
286			compatible = "simple-bus";
287			#size-cells = <1>;
288			#address-cells = <1>;
289			ranges = <0x51000000 0x51000000 0x3000
290				  0x0	     0x20000000 0x10000000>;
291			/**
292			 * To enable PCI endpoint mode, disable the pcie1_rc
293			 * node and enable pcie1_ep mode.
294			 */
295			pcie1_rc: pcie@51000000 {
296				compatible = "ti,dra7-pcie";
297				reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
298				reg-names = "rc_dbics", "ti_conf", "config";
299				interrupts = <0 232 0x4>, <0 233 0x4>;
300				#address-cells = <3>;
301				#size-cells = <2>;
302				device_type = "pci";
303				ranges = <0x81000000 0 0          0x03000 0 0x00010000
304					  0x82000000 0 0x20013000 0x13000 0 0xffed000>;
305				bus-range = <0x00 0xff>;
306				#interrupt-cells = <1>;
307				num-lanes = <1>;
308				linux,pci-domain = <0>;
309				ti,hwmods = "pcie1";
310				phys = <&pcie1_phy>;
311				phy-names = "pcie-phy0";
312				interrupt-map-mask = <0 0 0 7>;
313				interrupt-map = <0 0 0 1 &pcie1_intc 1>,
314						<0 0 0 2 &pcie1_intc 2>,
315						<0 0 0 3 &pcie1_intc 3>,
316						<0 0 0 4 &pcie1_intc 4>;
317				status = "disabled";
318				pcie1_intc: interrupt-controller {
319					interrupt-controller;
320					#address-cells = <0>;
321					#interrupt-cells = <1>;
322				};
323			};
324
325			pcie1_ep: pcie_ep@51000000 {
326				compatible = "ti,dra7-pcie-ep";
327				reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
328				reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
329				interrupts = <0 232 0x4>;
330				num-lanes = <1>;
331				num-ib-windows = <4>;
332				num-ob-windows = <16>;
333				ti,hwmods = "pcie1";
334				phys = <&pcie1_phy>;
335				phy-names = "pcie-phy0";
336				ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
337				status = "disabled";
338			};
339		};
340
341		axi@1 {
342			compatible = "simple-bus";
343			#size-cells = <1>;
344			#address-cells = <1>;
345			ranges = <0x51800000 0x51800000 0x3000
346				  0x0	     0x30000000 0x10000000>;
347			status = "disabled";
348			pcie@51800000 {
349				compatible = "ti,dra7-pcie";
350				reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
351				reg-names = "rc_dbics", "ti_conf", "config";
352				interrupts = <0 355 0x4>, <0 356 0x4>;
353				#address-cells = <3>;
354				#size-cells = <2>;
355				device_type = "pci";
356				ranges = <0x81000000 0 0          0x03000 0 0x00010000
357					  0x82000000 0 0x30013000 0x13000 0 0xffed000>;
358				bus-range = <0x00 0xff>;
359				#interrupt-cells = <1>;
360				num-lanes = <1>;
361				linux,pci-domain = <1>;
362				ti,hwmods = "pcie2";
363				phys = <&pcie2_phy>;
364				phy-names = "pcie-phy0";
365				interrupt-map-mask = <0 0 0 7>;
366				interrupt-map = <0 0 0 1 &pcie2_intc 1>,
367						<0 0 0 2 &pcie2_intc 2>,
368						<0 0 0 3 &pcie2_intc 3>,
369						<0 0 0 4 &pcie2_intc 4>;
370				pcie2_intc: interrupt-controller {
371					interrupt-controller;
372					#address-cells = <0>;
373					#interrupt-cells = <1>;
374				};
375			};
376		};
377
378		ocmcram1: ocmcram@40300000 {
379			compatible = "mmio-sram";
380			reg = <0x40300000 0x80000>;
381			ranges = <0x0 0x40300000 0x80000>;
382			#address-cells = <1>;
383			#size-cells = <1>;
384			/*
385			 * This is a placeholder for an optional reserved
386			 * region for use by secure software. The size
387			 * of this region is not known until runtime so it
388			 * is set as zero to either be updated to reserve
389			 * space or left unchanged to leave all SRAM for use.
390			 * On HS parts that that require the reserved region
391			 * either the bootloader can update the size to
392			 * the required amount or the node can be overridden
393			 * from the board dts file for the secure platform.
394			 */
395			sram-hs@0 {
396				compatible = "ti,secure-ram";
397				reg = <0x0 0x0>;
398			};
399		};
400
401		/*
402		 * NOTE: ocmcram2 and ocmcram3 are not available on all
403		 * DRA7xx and AM57xx variants. Confirm availability in
404		 * the data manual for the exact part number in use
405		 * before enabling these nodes in the board dts file.
406		 */
407		ocmcram2: ocmcram@40400000 {
408			status = "disabled";
409			compatible = "mmio-sram";
410			reg = <0x40400000 0x100000>;
411			ranges = <0x0 0x40400000 0x100000>;
412			#address-cells = <1>;
413			#size-cells = <1>;
414		};
415
416		ocmcram3: ocmcram@40500000 {
417			status = "disabled";
418			compatible = "mmio-sram";
419			reg = <0x40500000 0x100000>;
420			ranges = <0x0 0x40500000 0x100000>;
421			#address-cells = <1>;
422			#size-cells = <1>;
423		};
424
425		bandgap: bandgap@4a0021e0 {
426			reg = <0x4a0021e0 0xc
427				0x4a00232c 0xc
428				0x4a002380 0x2c
429				0x4a0023C0 0x3c
430				0x4a002564 0x8
431				0x4a002574 0x50>;
432				compatible = "ti,dra752-bandgap";
433				interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
434				#thermal-sensor-cells = <1>;
435		};
436
437		dsp1_system: dsp_system@40d00000 {
438			compatible = "syscon";
439			reg = <0x40d00000 0x100>;
440		};
441
442		dra7_iodelay_core: padconf@4844a000 {
443			compatible = "ti,dra7-iodelay";
444			reg = <0x4844a000 0x0d1c>;
445			#address-cells = <1>;
446			#size-cells = <0>;
447			#pinctrl-cells = <2>;
448		};
449
450		sdma: dma-controller@4a056000 {
451			compatible = "ti,omap4430-sdma";
452			reg = <0x4a056000 0x1000>;
453			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
454				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
455				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
456				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
457			#dma-cells = <1>;
458			dma-channels = <32>;
459			dma-requests = <127>;
460		};
461
462		edma: edma@43300000 {
463			compatible = "ti,edma3-tpcc";
464			ti,hwmods = "tpcc";
465			reg = <0x43300000 0x100000>;
466			reg-names = "edma3_cc";
467			interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
468				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
469				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
470			interrupt-names = "edma3_ccint", "edma3_mperr",
471					  "edma3_ccerrint";
472			dma-requests = <64>;
473			#dma-cells = <2>;
474
475			ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
476
477			/*
478			 * memcpy is disabled, can be enabled with:
479			 * ti,edma-memcpy-channels = <20 21>;
480			 * for example. Note that these channels need to be
481			 * masked in the xbar as well.
482			 */
483		};
484
485		edma_tptc0: tptc@43400000 {
486			compatible = "ti,edma3-tptc";
487			ti,hwmods = "tptc0";
488			reg =	<0x43400000 0x100000>;
489			interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
490			interrupt-names = "edma3_tcerrint";
491		};
492
493		edma_tptc1: tptc@43500000 {
494			compatible = "ti,edma3-tptc";
495			ti,hwmods = "tptc1";
496			reg =	<0x43500000 0x100000>;
497			interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
498			interrupt-names = "edma3_tcerrint";
499		};
500
501		gpio1: gpio@4ae10000 {
502			compatible = "ti,omap4-gpio";
503			reg = <0x4ae10000 0x200>;
504			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
505			ti,hwmods = "gpio1";
506			gpio-controller;
507			#gpio-cells = <2>;
508			interrupt-controller;
509			#interrupt-cells = <2>;
510		};
511
512		gpio2: gpio@48055000 {
513			compatible = "ti,omap4-gpio";
514			reg = <0x48055000 0x200>;
515			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
516			ti,hwmods = "gpio2";
517			gpio-controller;
518			#gpio-cells = <2>;
519			interrupt-controller;
520			#interrupt-cells = <2>;
521		};
522
523		gpio3: gpio@48057000 {
524			compatible = "ti,omap4-gpio";
525			reg = <0x48057000 0x200>;
526			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
527			ti,hwmods = "gpio3";
528			gpio-controller;
529			#gpio-cells = <2>;
530			interrupt-controller;
531			#interrupt-cells = <2>;
532		};
533
534		gpio4: gpio@48059000 {
535			compatible = "ti,omap4-gpio";
536			reg = <0x48059000 0x200>;
537			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
538			ti,hwmods = "gpio4";
539			gpio-controller;
540			#gpio-cells = <2>;
541			interrupt-controller;
542			#interrupt-cells = <2>;
543		};
544
545		gpio5: gpio@4805b000 {
546			compatible = "ti,omap4-gpio";
547			reg = <0x4805b000 0x200>;
548			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
549			ti,hwmods = "gpio5";
550			gpio-controller;
551			#gpio-cells = <2>;
552			interrupt-controller;
553			#interrupt-cells = <2>;
554		};
555
556		gpio6: gpio@4805d000 {
557			compatible = "ti,omap4-gpio";
558			reg = <0x4805d000 0x200>;
559			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
560			ti,hwmods = "gpio6";
561			gpio-controller;
562			#gpio-cells = <2>;
563			interrupt-controller;
564			#interrupt-cells = <2>;
565		};
566
567		gpio7: gpio@48051000 {
568			compatible = "ti,omap4-gpio";
569			reg = <0x48051000 0x200>;
570			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
571			ti,hwmods = "gpio7";
572			gpio-controller;
573			#gpio-cells = <2>;
574			interrupt-controller;
575			#interrupt-cells = <2>;
576		};
577
578		gpio8: gpio@48053000 {
579			compatible = "ti,omap4-gpio";
580			reg = <0x48053000 0x200>;
581			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
582			ti,hwmods = "gpio8";
583			gpio-controller;
584			#gpio-cells = <2>;
585			interrupt-controller;
586			#interrupt-cells = <2>;
587		};
588
589		uart1: serial@4806a000 {
590			compatible = "ti,dra742-uart", "ti,omap4-uart";
591			reg = <0x4806a000 0x100>;
592			interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
593			ti,hwmods = "uart1";
594			clock-frequency = <48000000>;
595			status = "disabled";
596			dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
597			dma-names = "tx", "rx";
598		};
599
600		uart2: serial@4806c000 {
601			compatible = "ti,dra742-uart", "ti,omap4-uart";
602			reg = <0x4806c000 0x100>;
603			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
604			ti,hwmods = "uart2";
605			clock-frequency = <48000000>;
606			status = "disabled";
607			dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
608			dma-names = "tx", "rx";
609		};
610
611		uart3: serial@48020000 {
612			compatible = "ti,dra742-uart", "ti,omap4-uart";
613			reg = <0x48020000 0x100>;
614			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
615			ti,hwmods = "uart3";
616			clock-frequency = <48000000>;
617			status = "disabled";
618			dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
619			dma-names = "tx", "rx";
620		};
621
622		uart4: serial@4806e000 {
623			compatible = "ti,dra742-uart", "ti,omap4-uart";
624			reg = <0x4806e000 0x100>;
625			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
626			ti,hwmods = "uart4";
627			clock-frequency = <48000000>;
628                        status = "disabled";
629			dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
630			dma-names = "tx", "rx";
631		};
632
633		uart5: serial@48066000 {
634			compatible = "ti,dra742-uart", "ti,omap4-uart";
635			reg = <0x48066000 0x100>;
636			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
637			ti,hwmods = "uart5";
638			clock-frequency = <48000000>;
639			status = "disabled";
640			dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
641			dma-names = "tx", "rx";
642		};
643
644		uart6: serial@48068000 {
645			compatible = "ti,dra742-uart", "ti,omap4-uart";
646			reg = <0x48068000 0x100>;
647			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
648			ti,hwmods = "uart6";
649			clock-frequency = <48000000>;
650			status = "disabled";
651			dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
652			dma-names = "tx", "rx";
653		};
654
655		uart7: serial@48420000 {
656			compatible = "ti,dra742-uart", "ti,omap4-uart";
657			reg = <0x48420000 0x100>;
658			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
659			ti,hwmods = "uart7";
660			clock-frequency = <48000000>;
661			status = "disabled";
662		};
663
664		uart8: serial@48422000 {
665			compatible = "ti,dra742-uart", "ti,omap4-uart";
666			reg = <0x48422000 0x100>;
667			interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
668			ti,hwmods = "uart8";
669			clock-frequency = <48000000>;
670			status = "disabled";
671		};
672
673		uart9: serial@48424000 {
674			compatible = "ti,dra742-uart", "ti,omap4-uart";
675			reg = <0x48424000 0x100>;
676			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
677			ti,hwmods = "uart9";
678			clock-frequency = <48000000>;
679			status = "disabled";
680		};
681
682		uart10: serial@4ae2b000 {
683			compatible = "ti,dra742-uart", "ti,omap4-uart";
684			reg = <0x4ae2b000 0x100>;
685			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
686			ti,hwmods = "uart10";
687			clock-frequency = <48000000>;
688			status = "disabled";
689		};
690
691		mailbox1: mailbox@4a0f4000 {
692			compatible = "ti,omap4-mailbox";
693			reg = <0x4a0f4000 0x200>;
694			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
695				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
696				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
697			ti,hwmods = "mailbox1";
698			#mbox-cells = <1>;
699			ti,mbox-num-users = <3>;
700			ti,mbox-num-fifos = <8>;
701			status = "disabled";
702		};
703
704		mailbox2: mailbox@4883a000 {
705			compatible = "ti,omap4-mailbox";
706			reg = <0x4883a000 0x200>;
707			interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
708				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
709				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
710				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
711			ti,hwmods = "mailbox2";
712			#mbox-cells = <1>;
713			ti,mbox-num-users = <4>;
714			ti,mbox-num-fifos = <12>;
715			status = "disabled";
716		};
717
718		mailbox3: mailbox@4883c000 {
719			compatible = "ti,omap4-mailbox";
720			reg = <0x4883c000 0x200>;
721			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
722				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
723				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
724				     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
725			ti,hwmods = "mailbox3";
726			#mbox-cells = <1>;
727			ti,mbox-num-users = <4>;
728			ti,mbox-num-fifos = <12>;
729			status = "disabled";
730		};
731
732		mailbox4: mailbox@4883e000 {
733			compatible = "ti,omap4-mailbox";
734			reg = <0x4883e000 0x200>;
735			interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
736				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
737				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
738				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
739			ti,hwmods = "mailbox4";
740			#mbox-cells = <1>;
741			ti,mbox-num-users = <4>;
742			ti,mbox-num-fifos = <12>;
743			status = "disabled";
744		};
745
746		mailbox5: mailbox@48840000 {
747			compatible = "ti,omap4-mailbox";
748			reg = <0x48840000 0x200>;
749			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
750				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
751				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
752				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
753			ti,hwmods = "mailbox5";
754			#mbox-cells = <1>;
755			ti,mbox-num-users = <4>;
756			ti,mbox-num-fifos = <12>;
757			status = "disabled";
758		};
759
760		mailbox6: mailbox@48842000 {
761			compatible = "ti,omap4-mailbox";
762			reg = <0x48842000 0x200>;
763			interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
764				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
765				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
766				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
767			ti,hwmods = "mailbox6";
768			#mbox-cells = <1>;
769			ti,mbox-num-users = <4>;
770			ti,mbox-num-fifos = <12>;
771			status = "disabled";
772		};
773
774		mailbox7: mailbox@48844000 {
775			compatible = "ti,omap4-mailbox";
776			reg = <0x48844000 0x200>;
777			interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
778				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
779				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
780				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
781			ti,hwmods = "mailbox7";
782			#mbox-cells = <1>;
783			ti,mbox-num-users = <4>;
784			ti,mbox-num-fifos = <12>;
785			status = "disabled";
786		};
787
788		mailbox8: mailbox@48846000 {
789			compatible = "ti,omap4-mailbox";
790			reg = <0x48846000 0x200>;
791			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
792				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
793				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
794				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
795			ti,hwmods = "mailbox8";
796			#mbox-cells = <1>;
797			ti,mbox-num-users = <4>;
798			ti,mbox-num-fifos = <12>;
799			status = "disabled";
800		};
801
802		mailbox9: mailbox@4885e000 {
803			compatible = "ti,omap4-mailbox";
804			reg = <0x4885e000 0x200>;
805			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
806				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
807				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
808				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
809			ti,hwmods = "mailbox9";
810			#mbox-cells = <1>;
811			ti,mbox-num-users = <4>;
812			ti,mbox-num-fifos = <12>;
813			status = "disabled";
814		};
815
816		mailbox10: mailbox@48860000 {
817			compatible = "ti,omap4-mailbox";
818			reg = <0x48860000 0x200>;
819			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
820				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
821				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
822				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
823			ti,hwmods = "mailbox10";
824			#mbox-cells = <1>;
825			ti,mbox-num-users = <4>;
826			ti,mbox-num-fifos = <12>;
827			status = "disabled";
828		};
829
830		mailbox11: mailbox@48862000 {
831			compatible = "ti,omap4-mailbox";
832			reg = <0x48862000 0x200>;
833			interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
834				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
835				     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
836				     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
837			ti,hwmods = "mailbox11";
838			#mbox-cells = <1>;
839			ti,mbox-num-users = <4>;
840			ti,mbox-num-fifos = <12>;
841			status = "disabled";
842		};
843
844		mailbox12: mailbox@48864000 {
845			compatible = "ti,omap4-mailbox";
846			reg = <0x48864000 0x200>;
847			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
848				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
849				     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
850				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
851			ti,hwmods = "mailbox12";
852			#mbox-cells = <1>;
853			ti,mbox-num-users = <4>;
854			ti,mbox-num-fifos = <12>;
855			status = "disabled";
856		};
857
858		mailbox13: mailbox@48802000 {
859			compatible = "ti,omap4-mailbox";
860			reg = <0x48802000 0x200>;
861			interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
862				     <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
863				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
864				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
865			ti,hwmods = "mailbox13";
866			#mbox-cells = <1>;
867			ti,mbox-num-users = <4>;
868			ti,mbox-num-fifos = <12>;
869			status = "disabled";
870		};
871
872		timer1: timer@4ae18000 {
873			compatible = "ti,omap5430-timer";
874			reg = <0x4ae18000 0x80>;
875			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
876			ti,hwmods = "timer1";
877			ti,timer-alwon;
878		};
879
880		timer2: timer@48032000 {
881			compatible = "ti,omap5430-timer";
882			reg = <0x48032000 0x80>;
883			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
884			ti,hwmods = "timer2";
885		};
886
887		timer3: timer@48034000 {
888			compatible = "ti,omap5430-timer";
889			reg = <0x48034000 0x80>;
890			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
891			ti,hwmods = "timer3";
892		};
893
894		timer4: timer@48036000 {
895			compatible = "ti,omap5430-timer";
896			reg = <0x48036000 0x80>;
897			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
898			ti,hwmods = "timer4";
899		};
900
901		timer5: timer@48820000 {
902			compatible = "ti,omap5430-timer";
903			reg = <0x48820000 0x80>;
904			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
905			ti,hwmods = "timer5";
906		};
907
908		timer6: timer@48822000 {
909			compatible = "ti,omap5430-timer";
910			reg = <0x48822000 0x80>;
911			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
912			ti,hwmods = "timer6";
913		};
914
915		timer7: timer@48824000 {
916			compatible = "ti,omap5430-timer";
917			reg = <0x48824000 0x80>;
918			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
919			ti,hwmods = "timer7";
920		};
921
922		timer8: timer@48826000 {
923			compatible = "ti,omap5430-timer";
924			reg = <0x48826000 0x80>;
925			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
926			ti,hwmods = "timer8";
927		};
928
929		timer9: timer@4803e000 {
930			compatible = "ti,omap5430-timer";
931			reg = <0x4803e000 0x80>;
932			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
933			ti,hwmods = "timer9";
934		};
935
936		timer10: timer@48086000 {
937			compatible = "ti,omap5430-timer";
938			reg = <0x48086000 0x80>;
939			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
940			ti,hwmods = "timer10";
941		};
942
943		timer11: timer@48088000 {
944			compatible = "ti,omap5430-timer";
945			reg = <0x48088000 0x80>;
946			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
947			ti,hwmods = "timer11";
948		};
949
950		timer12: timer@4ae20000 {
951			compatible = "ti,omap5430-timer";
952			reg = <0x4ae20000 0x80>;
953			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
954			ti,hwmods = "timer12";
955			ti,timer-alwon;
956			ti,timer-secure;
957		};
958
959		timer13: timer@48828000 {
960			compatible = "ti,omap5430-timer";
961			reg = <0x48828000 0x80>;
962			interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
963			ti,hwmods = "timer13";
964		};
965
966		timer14: timer@4882a000 {
967			compatible = "ti,omap5430-timer";
968			reg = <0x4882a000 0x80>;
969			interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
970			ti,hwmods = "timer14";
971		};
972
973		timer15: timer@4882c000 {
974			compatible = "ti,omap5430-timer";
975			reg = <0x4882c000 0x80>;
976			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
977			ti,hwmods = "timer15";
978		};
979
980		timer16: timer@4882e000 {
981			compatible = "ti,omap5430-timer";
982			reg = <0x4882e000 0x80>;
983			interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
984			ti,hwmods = "timer16";
985		};
986
987		wdt2: wdt@4ae14000 {
988			compatible = "ti,omap3-wdt";
989			reg = <0x4ae14000 0x80>;
990			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
991			ti,hwmods = "wd_timer2";
992		};
993
994		hwspinlock: spinlock@4a0f6000 {
995			compatible = "ti,omap4-hwspinlock";
996			reg = <0x4a0f6000 0x1000>;
997			ti,hwmods = "spinlock";
998			#hwlock-cells = <1>;
999		};
1000
1001		dmm@4e000000 {
1002			compatible = "ti,omap5-dmm";
1003			reg = <0x4e000000 0x800>;
1004			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1005			ti,hwmods = "dmm";
1006		};
1007
1008		i2c1: i2c@48070000 {
1009			compatible = "ti,omap4-i2c";
1010			reg = <0x48070000 0x100>;
1011			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1012			#address-cells = <1>;
1013			#size-cells = <0>;
1014			ti,hwmods = "i2c1";
1015			status = "disabled";
1016		};
1017
1018		i2c2: i2c@48072000 {
1019			compatible = "ti,omap4-i2c";
1020			reg = <0x48072000 0x100>;
1021			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1022			#address-cells = <1>;
1023			#size-cells = <0>;
1024			ti,hwmods = "i2c2";
1025			status = "disabled";
1026		};
1027
1028		i2c3: i2c@48060000 {
1029			compatible = "ti,omap4-i2c";
1030			reg = <0x48060000 0x100>;
1031			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1032			#address-cells = <1>;
1033			#size-cells = <0>;
1034			ti,hwmods = "i2c3";
1035			status = "disabled";
1036		};
1037
1038		i2c4: i2c@4807a000 {
1039			compatible = "ti,omap4-i2c";
1040			reg = <0x4807a000 0x100>;
1041			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1042			#address-cells = <1>;
1043			#size-cells = <0>;
1044			ti,hwmods = "i2c4";
1045			status = "disabled";
1046		};
1047
1048		i2c5: i2c@4807c000 {
1049			compatible = "ti,omap4-i2c";
1050			reg = <0x4807c000 0x100>;
1051			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1052			#address-cells = <1>;
1053			#size-cells = <0>;
1054			ti,hwmods = "i2c5";
1055			status = "disabled";
1056		};
1057
1058		mmc1: mmc@4809c000 {
1059			compatible = "ti,omap4-hsmmc";
1060			reg = <0x4809c000 0x400>;
1061			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1062			ti,hwmods = "mmc1";
1063			ti,dual-volt;
1064			ti,needs-special-reset;
1065			dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
1066			dma-names = "tx", "rx";
1067			status = "disabled";
1068			pbias-supply = <&pbias_mmc_reg>;
1069			max-frequency = <192000000>;
1070		};
1071
1072		mmc2: mmc@480b4000 {
1073			compatible = "ti,omap4-hsmmc";
1074			reg = <0x480b4000 0x400>;
1075			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1076			ti,hwmods = "mmc2";
1077			ti,needs-special-reset;
1078			dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
1079			dma-names = "tx", "rx";
1080			status = "disabled";
1081			max-frequency = <192000000>;
1082		};
1083
1084		mmc3: mmc@480ad000 {
1085			compatible = "ti,omap4-hsmmc";
1086			reg = <0x480ad000 0x400>;
1087			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1088			ti,hwmods = "mmc3";
1089			ti,needs-special-reset;
1090			dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
1091			dma-names = "tx", "rx";
1092			status = "disabled";
1093			/* Errata i887 limits max-frequency of MMC3 to 64 MHz */
1094			max-frequency = <64000000>;
1095		};
1096
1097		mmc4: mmc@480d1000 {
1098			compatible = "ti,omap4-hsmmc";
1099			reg = <0x480d1000 0x400>;
1100			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1101			ti,hwmods = "mmc4";
1102			ti,needs-special-reset;
1103			dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
1104			dma-names = "tx", "rx";
1105			status = "disabled";
1106			max-frequency = <192000000>;
1107		};
1108
1109		mmu0_dsp1: mmu@40d01000 {
1110			compatible = "ti,dra7-dsp-iommu";
1111			reg = <0x40d01000 0x100>;
1112			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1113			ti,hwmods = "mmu0_dsp1";
1114			#iommu-cells = <0>;
1115			ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1116			status = "disabled";
1117		};
1118
1119		mmu1_dsp1: mmu@40d02000 {
1120			compatible = "ti,dra7-dsp-iommu";
1121			reg = <0x40d02000 0x100>;
1122			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1123			ti,hwmods = "mmu1_dsp1";
1124			#iommu-cells = <0>;
1125			ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1126			status = "disabled";
1127		};
1128
1129		mmu_ipu1: mmu@58882000 {
1130			compatible = "ti,dra7-iommu";
1131			reg = <0x58882000 0x100>;
1132			interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1133			ti,hwmods = "mmu_ipu1";
1134			#iommu-cells = <0>;
1135			ti,iommu-bus-err-back;
1136			status = "disabled";
1137		};
1138
1139		mmu_ipu2: mmu@55082000 {
1140			compatible = "ti,dra7-iommu";
1141			reg = <0x55082000 0x100>;
1142			interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1143			ti,hwmods = "mmu_ipu2";
1144			#iommu-cells = <0>;
1145			ti,iommu-bus-err-back;
1146			status = "disabled";
1147		};
1148
1149		abb_mpu: regulator-abb-mpu {
1150			compatible = "ti,abb-v3";
1151			regulator-name = "abb_mpu";
1152			#address-cells = <0>;
1153			#size-cells = <0>;
1154			clocks = <&sys_clkin1>;
1155			ti,settling-time = <50>;
1156			ti,clock-cycles = <16>;
1157
1158			reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1159			      <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1160			      <0x4ae0c158 0x4>;
1161			reg-names = "setup-address", "control-address",
1162				    "int-address", "efuse-address",
1163				    "ldo-address";
1164			ti,tranxdone-status-mask = <0x80>;
1165			/* LDOVBBMPU_FBB_MUX_CTRL */
1166			ti,ldovbb-override-mask = <0x400>;
1167			/* LDOVBBMPU_FBB_VSET_OUT */
1168			ti,ldovbb-vset-mask = <0x1F>;
1169
1170			/*
1171			 * NOTE: only FBB mode used but actual vset will
1172			 * determine final biasing
1173			 */
1174			ti,abb_info = <
1175			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
1176			1060000		0	0x0	0 0x02000000 0x01F00000
1177			1160000		0	0x4	0 0x02000000 0x01F00000
1178			1210000		0	0x8	0 0x02000000 0x01F00000
1179			>;
1180		};
1181
1182		abb_ivahd: regulator-abb-ivahd {
1183			compatible = "ti,abb-v3";
1184			regulator-name = "abb_ivahd";
1185			#address-cells = <0>;
1186			#size-cells = <0>;
1187			clocks = <&sys_clkin1>;
1188			ti,settling-time = <50>;
1189			ti,clock-cycles = <16>;
1190
1191			reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1192			      <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1193			      <0x4a002470 0x4>;
1194			reg-names = "setup-address", "control-address",
1195				    "int-address", "efuse-address",
1196				    "ldo-address";
1197			ti,tranxdone-status-mask = <0x40000000>;
1198			/* LDOVBBIVA_FBB_MUX_CTRL */
1199			ti,ldovbb-override-mask = <0x400>;
1200			/* LDOVBBIVA_FBB_VSET_OUT */
1201			ti,ldovbb-vset-mask = <0x1F>;
1202
1203			/*
1204			 * NOTE: only FBB mode used but actual vset will
1205			 * determine final biasing
1206			 */
1207			ti,abb_info = <
1208			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
1209			1055000		0	0x0	0 0x02000000 0x01F00000
1210			1150000		0	0x4	0 0x02000000 0x01F00000
1211			1250000		0	0x8	0 0x02000000 0x01F00000
1212			>;
1213		};
1214
1215		abb_dspeve: regulator-abb-dspeve {
1216			compatible = "ti,abb-v3";
1217			regulator-name = "abb_dspeve";
1218			#address-cells = <0>;
1219			#size-cells = <0>;
1220			clocks = <&sys_clkin1>;
1221			ti,settling-time = <50>;
1222			ti,clock-cycles = <16>;
1223
1224			reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1225			      <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1226			      <0x4a00246c 0x4>;
1227			reg-names = "setup-address", "control-address",
1228				    "int-address", "efuse-address",
1229				    "ldo-address";
1230			ti,tranxdone-status-mask = <0x20000000>;
1231			/* LDOVBBDSPEVE_FBB_MUX_CTRL */
1232			ti,ldovbb-override-mask = <0x400>;
1233			/* LDOVBBDSPEVE_FBB_VSET_OUT */
1234			ti,ldovbb-vset-mask = <0x1F>;
1235
1236			/*
1237			 * NOTE: only FBB mode used but actual vset will
1238			 * determine final biasing
1239			 */
1240			ti,abb_info = <
1241			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
1242			1055000		0	0x0	0 0x02000000 0x01F00000
1243			1150000		0	0x4	0 0x02000000 0x01F00000
1244			1250000		0	0x8	0 0x02000000 0x01F00000
1245			>;
1246		};
1247
1248		abb_gpu: regulator-abb-gpu {
1249			compatible = "ti,abb-v3";
1250			regulator-name = "abb_gpu";
1251			#address-cells = <0>;
1252			#size-cells = <0>;
1253			clocks = <&sys_clkin1>;
1254			ti,settling-time = <50>;
1255			ti,clock-cycles = <16>;
1256
1257			reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1258			      <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1259			      <0x4ae0c154 0x4>;
1260			reg-names = "setup-address", "control-address",
1261				    "int-address", "efuse-address",
1262				    "ldo-address";
1263			ti,tranxdone-status-mask = <0x10000000>;
1264			/* LDOVBBGPU_FBB_MUX_CTRL */
1265			ti,ldovbb-override-mask = <0x400>;
1266			/* LDOVBBGPU_FBB_VSET_OUT */
1267			ti,ldovbb-vset-mask = <0x1F>;
1268
1269			/*
1270			 * NOTE: only FBB mode used but actual vset will
1271			 * determine final biasing
1272			 */
1273			ti,abb_info = <
1274			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
1275			1090000		0	0x0	0 0x02000000 0x01F00000
1276			1210000		0	0x4	0 0x02000000 0x01F00000
1277			1280000		0	0x8	0 0x02000000 0x01F00000
1278			>;
1279		};
1280
1281		mcspi1: spi@48098000 {
1282			compatible = "ti,omap4-mcspi";
1283			reg = <0x48098000 0x200>;
1284			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1285			#address-cells = <1>;
1286			#size-cells = <0>;
1287			ti,hwmods = "mcspi1";
1288			ti,spi-num-cs = <4>;
1289			dmas = <&sdma_xbar 35>,
1290			       <&sdma_xbar 36>,
1291			       <&sdma_xbar 37>,
1292			       <&sdma_xbar 38>,
1293			       <&sdma_xbar 39>,
1294			       <&sdma_xbar 40>,
1295			       <&sdma_xbar 41>,
1296			       <&sdma_xbar 42>;
1297			dma-names = "tx0", "rx0", "tx1", "rx1",
1298				    "tx2", "rx2", "tx3", "rx3";
1299			status = "disabled";
1300		};
1301
1302		mcspi2: spi@4809a000 {
1303			compatible = "ti,omap4-mcspi";
1304			reg = <0x4809a000 0x200>;
1305			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1306			#address-cells = <1>;
1307			#size-cells = <0>;
1308			ti,hwmods = "mcspi2";
1309			ti,spi-num-cs = <2>;
1310			dmas = <&sdma_xbar 43>,
1311			       <&sdma_xbar 44>,
1312			       <&sdma_xbar 45>,
1313			       <&sdma_xbar 46>;
1314			dma-names = "tx0", "rx0", "tx1", "rx1";
1315			status = "disabled";
1316		};
1317
1318		mcspi3: spi@480b8000 {
1319			compatible = "ti,omap4-mcspi";
1320			reg = <0x480b8000 0x200>;
1321			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1322			#address-cells = <1>;
1323			#size-cells = <0>;
1324			ti,hwmods = "mcspi3";
1325			ti,spi-num-cs = <2>;
1326			dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1327			dma-names = "tx0", "rx0";
1328			status = "disabled";
1329		};
1330
1331		mcspi4: spi@480ba000 {
1332			compatible = "ti,omap4-mcspi";
1333			reg = <0x480ba000 0x200>;
1334			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1335			#address-cells = <1>;
1336			#size-cells = <0>;
1337			ti,hwmods = "mcspi4";
1338			ti,spi-num-cs = <1>;
1339			dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1340			dma-names = "tx0", "rx0";
1341			status = "disabled";
1342		};
1343
1344		qspi: qspi@4b300000 {
1345			compatible = "ti,dra7xxx-qspi";
1346			reg = <0x4b300000 0x100>,
1347			      <0x5c000000 0x4000000>;
1348			reg-names = "qspi_base", "qspi_mmap";
1349			syscon-chipselects = <&scm_conf 0x558>;
1350			#address-cells = <1>;
1351			#size-cells = <0>;
1352			ti,hwmods = "qspi";
1353			clocks = <&qspi_gfclk_div>;
1354			clock-names = "fck";
1355			num-cs = <4>;
1356			interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1357			status = "disabled";
1358		};
1359
1360		/* OCP2SCP3 */
1361		ocp2scp@4a090000 {
1362			compatible = "ti,omap-ocp2scp";
1363			#address-cells = <1>;
1364			#size-cells = <1>;
1365			ranges;
1366			reg = <0x4a090000 0x20>;
1367			ti,hwmods = "ocp2scp3";
1368			sata_phy: phy@4A096000 {
1369				compatible = "ti,phy-pipe3-sata";
1370				reg = <0x4A096000 0x80>, /* phy_rx */
1371				      <0x4A096400 0x64>, /* phy_tx */
1372				      <0x4A096800 0x40>; /* pll_ctrl */
1373				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1374				syscon-phy-power = <&scm_conf 0x374>;
1375				clocks = <&sys_clkin1>, <&sata_ref_clk>;
1376				clock-names = "sysclk", "refclk";
1377				syscon-pllreset = <&scm_conf 0x3fc>;
1378				#phy-cells = <0>;
1379			};
1380
1381			pcie1_phy: pciephy@4a094000 {
1382				compatible = "ti,phy-pipe3-pcie";
1383				reg = <0x4a094000 0x80>, /* phy_rx */
1384				      <0x4a094400 0x64>; /* phy_tx */
1385				reg-names = "phy_rx", "phy_tx";
1386				syscon-phy-power = <&scm_conf_pcie 0x1c>;
1387				syscon-pcs = <&scm_conf_pcie 0x10>;
1388				clocks = <&dpll_pcie_ref_ck>,
1389					 <&dpll_pcie_ref_m2ldo_ck>,
1390					 <&optfclk_pciephy1_32khz>,
1391					 <&optfclk_pciephy1_clk>,
1392					 <&optfclk_pciephy1_div_clk>,
1393					 <&optfclk_pciephy_div>,
1394					 <&sys_clkin1>;
1395				clock-names = "dpll_ref", "dpll_ref_m2",
1396					      "wkupclk", "refclk",
1397					      "div-clk", "phy-div", "sysclk";
1398				#phy-cells = <0>;
1399			};
1400
1401			pcie2_phy: pciephy@4a095000 {
1402				compatible = "ti,phy-pipe3-pcie";
1403				reg = <0x4a095000 0x80>, /* phy_rx */
1404				      <0x4a095400 0x64>; /* phy_tx */
1405				reg-names = "phy_rx", "phy_tx";
1406				syscon-phy-power = <&scm_conf_pcie 0x20>;
1407				syscon-pcs = <&scm_conf_pcie 0x10>;
1408				clocks = <&dpll_pcie_ref_ck>,
1409					 <&dpll_pcie_ref_m2ldo_ck>,
1410					 <&optfclk_pciephy2_32khz>,
1411					 <&optfclk_pciephy2_clk>,
1412					 <&optfclk_pciephy2_div_clk>,
1413					 <&optfclk_pciephy_div>,
1414					 <&sys_clkin1>;
1415				clock-names = "dpll_ref", "dpll_ref_m2",
1416					      "wkupclk", "refclk",
1417					      "div-clk", "phy-div", "sysclk";
1418				#phy-cells = <0>;
1419				status = "disabled";
1420			};
1421		};
1422
1423		sata: sata@4a141100 {
1424			compatible = "snps,dwc-ahci";
1425			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1426			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1427			phys = <&sata_phy>;
1428			phy-names = "sata-phy";
1429			clocks = <&sata_ref_clk>;
1430			ti,hwmods = "sata";
1431			ports-implemented = <0x1>;
1432		};
1433
1434		rtc: rtc@48838000 {
1435			compatible = "ti,am3352-rtc";
1436			reg = <0x48838000 0x100>;
1437			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1438				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1439			ti,hwmods = "rtcss";
1440			clocks = <&sys_32k_ck>;
1441		};
1442
1443		/* OCP2SCP1 */
1444		ocp2scp@4a080000 {
1445			compatible = "ti,omap-ocp2scp";
1446			#address-cells = <1>;
1447			#size-cells = <1>;
1448			ranges;
1449			reg = <0x4a080000 0x20>;
1450			ti,hwmods = "ocp2scp1";
1451
1452			usb2_phy1: phy@4a084000 {
1453				compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1454				reg = <0x4a084000 0x400>;
1455				syscon-phy-power = <&scm_conf 0x300>;
1456				clocks = <&usb_phy1_always_on_clk32k>,
1457					 <&usb_otg_ss1_refclk960m>;
1458				clock-names =	"wkupclk",
1459						"refclk";
1460				#phy-cells = <0>;
1461			};
1462
1463			usb2_phy2: phy@4a085000 {
1464				compatible = "ti,dra7x-usb2-phy2",
1465					     "ti,omap-usb2";
1466				reg = <0x4a085000 0x400>;
1467				syscon-phy-power = <&scm_conf 0xe74>;
1468				clocks = <&usb_phy2_always_on_clk32k>,
1469					 <&usb_otg_ss2_refclk960m>;
1470				clock-names =	"wkupclk",
1471						"refclk";
1472				#phy-cells = <0>;
1473			};
1474
1475			usb3_phy1: phy@4a084400 {
1476				compatible = "ti,omap-usb3";
1477				reg = <0x4a084400 0x80>,
1478				      <0x4a084800 0x64>,
1479				      <0x4a084c00 0x40>;
1480				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1481				syscon-phy-power = <&scm_conf 0x370>;
1482				clocks = <&usb_phy3_always_on_clk32k>,
1483					 <&sys_clkin1>,
1484					 <&usb_otg_ss1_refclk960m>;
1485				clock-names =	"wkupclk",
1486						"sysclk",
1487						"refclk";
1488				#phy-cells = <0>;
1489			};
1490		};
1491
1492		omap_dwc3_1: omap_dwc3_1@48880000 {
1493			compatible = "ti,dwc3";
1494			ti,hwmods = "usb_otg_ss1";
1495			reg = <0x48880000 0x10000>;
1496			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1497			#address-cells = <1>;
1498			#size-cells = <1>;
1499			utmi-mode = <2>;
1500			ranges;
1501			usb1: usb@48890000 {
1502				compatible = "snps,dwc3";
1503				reg = <0x48890000 0x17000>;
1504				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1505					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1506					     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1507				interrupt-names = "peripheral",
1508						  "host",
1509						  "otg";
1510				phys = <&usb2_phy1>, <&usb3_phy1>;
1511				phy-names = "usb2-phy", "usb3-phy";
1512				maximum-speed = "super-speed";
1513				dr_mode = "otg";
1514				snps,dis_u3_susphy_quirk;
1515				snps,dis_u2_susphy_quirk;
1516			};
1517		};
1518
1519		omap_dwc3_2: omap_dwc3_2@488c0000 {
1520			compatible = "ti,dwc3";
1521			ti,hwmods = "usb_otg_ss2";
1522			reg = <0x488c0000 0x10000>;
1523			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1524			#address-cells = <1>;
1525			#size-cells = <1>;
1526			utmi-mode = <2>;
1527			ranges;
1528			usb2: usb@488d0000 {
1529				compatible = "snps,dwc3";
1530				reg = <0x488d0000 0x17000>;
1531				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1532					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1533					     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1534				interrupt-names = "peripheral",
1535						  "host",
1536						  "otg";
1537				phys = <&usb2_phy2>;
1538				phy-names = "usb2-phy";
1539				maximum-speed = "high-speed";
1540				dr_mode = "otg";
1541				snps,dis_u3_susphy_quirk;
1542				snps,dis_u2_susphy_quirk;
1543			};
1544		};
1545
1546		/* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1547		omap_dwc3_3: omap_dwc3_3@48900000 {
1548			compatible = "ti,dwc3";
1549			ti,hwmods = "usb_otg_ss3";
1550			reg = <0x48900000 0x10000>;
1551			interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1552			#address-cells = <1>;
1553			#size-cells = <1>;
1554			utmi-mode = <2>;
1555			ranges;
1556			status = "disabled";
1557			usb3: usb@48910000 {
1558				compatible = "snps,dwc3";
1559				reg = <0x48910000 0x17000>;
1560				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1561					     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1562					     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1563				interrupt-names = "peripheral",
1564						  "host",
1565						  "otg";
1566				maximum-speed = "high-speed";
1567				dr_mode = "otg";
1568				snps,dis_u3_susphy_quirk;
1569				snps,dis_u2_susphy_quirk;
1570			};
1571		};
1572
1573		elm: elm@48078000 {
1574			compatible = "ti,am3352-elm";
1575			reg = <0x48078000 0xfc0>;      /* device IO registers */
1576			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1577			ti,hwmods = "elm";
1578			status = "disabled";
1579		};
1580
1581		gpmc: gpmc@50000000 {
1582			compatible = "ti,am3352-gpmc";
1583			ti,hwmods = "gpmc";
1584			reg = <0x50000000 0x37c>;      /* device IO registers */
1585			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1586			dmas = <&edma_xbar 4 0>;
1587			dma-names = "rxtx";
1588			gpmc,num-cs = <8>;
1589			gpmc,num-waitpins = <2>;
1590			#address-cells = <2>;
1591			#size-cells = <1>;
1592			interrupt-controller;
1593			#interrupt-cells = <2>;
1594			gpio-controller;
1595			#gpio-cells = <2>;
1596			status = "disabled";
1597		};
1598
1599		atl: atl@4843c000 {
1600			compatible = "ti,dra7-atl";
1601			reg = <0x4843c000 0x3ff>;
1602			ti,hwmods = "atl";
1603			ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1604					     <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1605			clocks = <&atl_gfclk_mux>;
1606			clock-names = "fck";
1607			status = "disabled";
1608		};
1609
1610		mcasp1: mcasp@48460000 {
1611			compatible = "ti,dra7-mcasp-audio";
1612			ti,hwmods = "mcasp1";
1613			reg = <0x48460000 0x2000>,
1614			      <0x45800000 0x1000>;
1615			reg-names = "mpu","dat";
1616			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1617				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1618			interrupt-names = "tx", "rx";
1619			dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1620			dma-names = "tx", "rx";
1621			clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
1622				 <&mcasp1_ahclkr_mux>;
1623			clock-names = "fck", "ahclkx", "ahclkr";
1624			status = "disabled";
1625		};
1626
1627		mcasp2: mcasp@48464000 {
1628			compatible = "ti,dra7-mcasp-audio";
1629			ti,hwmods = "mcasp2";
1630			reg = <0x48464000 0x2000>,
1631			      <0x45c00000 0x1000>;
1632			reg-names = "mpu","dat";
1633			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1634				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1635			interrupt-names = "tx", "rx";
1636			dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1637			dma-names = "tx", "rx";
1638			clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
1639				 <&mcasp2_ahclkr_mux>;
1640			clock-names = "fck", "ahclkx", "ahclkr";
1641			status = "disabled";
1642		};
1643
1644		mcasp3: mcasp@48468000 {
1645			compatible = "ti,dra7-mcasp-audio";
1646			ti,hwmods = "mcasp3";
1647			reg = <0x48468000 0x2000>,
1648			      <0x46000000 0x1000>;
1649			reg-names = "mpu","dat";
1650			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1651				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1652			interrupt-names = "tx", "rx";
1653			dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1654			dma-names = "tx", "rx";
1655			clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1656			clock-names = "fck", "ahclkx";
1657			status = "disabled";
1658		};
1659
1660		mcasp4: mcasp@4846c000 {
1661			compatible = "ti,dra7-mcasp-audio";
1662			ti,hwmods = "mcasp4";
1663			reg = <0x4846c000 0x2000>,
1664			      <0x48436000 0x1000>;
1665			reg-names = "mpu","dat";
1666			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1667				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1668			interrupt-names = "tx", "rx";
1669			dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1670			dma-names = "tx", "rx";
1671			clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
1672			clock-names = "fck", "ahclkx";
1673			status = "disabled";
1674		};
1675
1676		mcasp5: mcasp@48470000 {
1677			compatible = "ti,dra7-mcasp-audio";
1678			ti,hwmods = "mcasp5";
1679			reg = <0x48470000 0x2000>,
1680			      <0x4843a000 0x1000>;
1681			reg-names = "mpu","dat";
1682			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1683				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1684			interrupt-names = "tx", "rx";
1685			dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1686			dma-names = "tx", "rx";
1687			clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
1688			clock-names = "fck", "ahclkx";
1689			status = "disabled";
1690		};
1691
1692		mcasp6: mcasp@48474000 {
1693			compatible = "ti,dra7-mcasp-audio";
1694			ti,hwmods = "mcasp6";
1695			reg = <0x48474000 0x2000>,
1696			      <0x4844c000 0x1000>;
1697			reg-names = "mpu","dat";
1698			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1699				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1700			interrupt-names = "tx", "rx";
1701			dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1702			dma-names = "tx", "rx";
1703			clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
1704			clock-names = "fck", "ahclkx";
1705			status = "disabled";
1706		};
1707
1708		mcasp7: mcasp@48478000 {
1709			compatible = "ti,dra7-mcasp-audio";
1710			ti,hwmods = "mcasp7";
1711			reg = <0x48478000 0x2000>,
1712			      <0x48450000 0x1000>;
1713			reg-names = "mpu","dat";
1714			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1715				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1716			interrupt-names = "tx", "rx";
1717			dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1718			dma-names = "tx", "rx";
1719			clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
1720			clock-names = "fck", "ahclkx";
1721			status = "disabled";
1722		};
1723
1724		mcasp8: mcasp@4847c000 {
1725			compatible = "ti,dra7-mcasp-audio";
1726			ti,hwmods = "mcasp8";
1727			reg = <0x4847c000 0x2000>,
1728			      <0x48454000 0x1000>;
1729			reg-names = "mpu","dat";
1730			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1731				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1732			interrupt-names = "tx", "rx";
1733			dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1734			dma-names = "tx", "rx";
1735			clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
1736			clock-names = "fck", "ahclkx";
1737			status = "disabled";
1738		};
1739
1740		crossbar_mpu: crossbar@4a002a48 {
1741			compatible = "ti,irq-crossbar";
1742			reg = <0x4a002a48 0x130>;
1743			interrupt-controller;
1744			interrupt-parent = <&wakeupgen>;
1745			#interrupt-cells = <3>;
1746			ti,max-irqs = <160>;
1747			ti,max-crossbar-sources = <MAX_SOURCES>;
1748			ti,reg-size = <2>;
1749			ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1750			ti,irqs-skip = <10 133 139 140>;
1751			ti,irqs-safe-map = <0>;
1752		};
1753
1754		mac: ethernet@48484000 {
1755			compatible = "ti,dra7-cpsw","ti,cpsw";
1756			ti,hwmods = "gmac";
1757			clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
1758			clock-names = "fck", "cpts";
1759			cpdma_channels = <8>;
1760			ale_entries = <1024>;
1761			bd_ram_size = <0x2000>;
1762			mac_control = <0x20>;
1763			slaves = <2>;
1764			active_slave = <0>;
1765			cpts_clock_mult = <0x784CFE14>;
1766			cpts_clock_shift = <29>;
1767			reg = <0x48484000 0x1000
1768			       0x48485200 0x2E00>;
1769			#address-cells = <1>;
1770			#size-cells = <1>;
1771
1772			/*
1773			 * Do not allow gating of cpsw clock as workaround
1774			 * for errata i877. Keeping internal clock disabled
1775			 * causes the device switching characteristics
1776			 * to degrade over time and eventually fail to meet
1777			 * the data manual delay time/skew specs.
1778			 */
1779			ti,no-idle;
1780
1781			/*
1782			 * rx_thresh_pend
1783			 * rx_pend
1784			 * tx_pend
1785			 * misc_pend
1786			 */
1787			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1788				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1789				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1790				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1791			ranges;
1792			syscon = <&scm_conf>;
1793			status = "disabled";
1794
1795			davinci_mdio: mdio@48485000 {
1796				compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1797				#address-cells = <1>;
1798				#size-cells = <0>;
1799				ti,hwmods = "davinci_mdio";
1800				bus_freq = <1000000>;
1801				reg = <0x48485000 0x100>;
1802			};
1803
1804			cpsw_emac0: slave@48480200 {
1805				/* Filled in by U-Boot */
1806				mac-address = [ 00 00 00 00 00 00 ];
1807			};
1808
1809			cpsw_emac1: slave@48480300 {
1810				/* Filled in by U-Boot */
1811				mac-address = [ 00 00 00 00 00 00 ];
1812			};
1813
1814			phy_sel: cpsw-phy-sel@4a002554 {
1815				compatible = "ti,dra7xx-cpsw-phy-sel";
1816				reg= <0x4a002554 0x4>;
1817				reg-names = "gmii-sel";
1818			};
1819		};
1820
1821		dcan1: can@481cc000 {
1822			compatible = "ti,dra7-d_can";
1823			ti,hwmods = "dcan1";
1824			reg = <0x4ae3c000 0x2000>;
1825			syscon-raminit = <&scm_conf 0x558 0>;
1826			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1827			clocks = <&dcan1_sys_clk_mux>;
1828			status = "disabled";
1829		};
1830
1831		dcan2: can@481d0000 {
1832			compatible = "ti,dra7-d_can";
1833			ti,hwmods = "dcan2";
1834			reg = <0x48480000 0x2000>;
1835			syscon-raminit = <&scm_conf 0x558 1>;
1836			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1837			clocks = <&sys_clkin1>;
1838			status = "disabled";
1839		};
1840
1841		dss: dss@58000000 {
1842			compatible = "ti,dra7-dss";
1843			/* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1844			/* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1845			status = "disabled";
1846			ti,hwmods = "dss_core";
1847			/* CTRL_CORE_DSS_PLL_CONTROL */
1848			syscon-pll-ctrl = <&scm_conf 0x538>;
1849			#address-cells = <1>;
1850			#size-cells = <1>;
1851			ranges;
1852
1853			dispc@58001000 {
1854				compatible = "ti,dra7-dispc";
1855				reg = <0x58001000 0x1000>;
1856				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1857				ti,hwmods = "dss_dispc";
1858				clocks = <&dss_dss_clk>;
1859				clock-names = "fck";
1860				/* CTRL_CORE_SMA_SW_1 */
1861				syscon-pol = <&scm_conf 0x534>;
1862			};
1863
1864			hdmi: encoder@58060000 {
1865				compatible = "ti,dra7-hdmi";
1866				reg = <0x58040000 0x200>,
1867				      <0x58040200 0x80>,
1868				      <0x58040300 0x80>,
1869				      <0x58060000 0x19000>;
1870				reg-names = "wp", "pll", "phy", "core";
1871				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1872				status = "disabled";
1873				ti,hwmods = "dss_hdmi";
1874				clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1875				clock-names = "fck", "sys_clk";
1876			};
1877		};
1878
1879		epwmss0: epwmss@4843e000 {
1880			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1881			reg = <0x4843e000 0x30>;
1882			ti,hwmods = "epwmss0";
1883			#address-cells = <1>;
1884			#size-cells = <1>;
1885			status = "disabled";
1886			ranges;
1887
1888			ehrpwm0: pwm@4843e200 {
1889				compatible = "ti,dra746-ehrpwm",
1890					     "ti,am3352-ehrpwm";
1891				#pwm-cells = <3>;
1892				reg = <0x4843e200 0x80>;
1893				clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1894				clock-names = "tbclk", "fck";
1895				status = "disabled";
1896			};
1897
1898			ecap0: ecap@4843e100 {
1899				compatible = "ti,dra746-ecap",
1900					     "ti,am3352-ecap";
1901				#pwm-cells = <3>;
1902				reg = <0x4843e100 0x80>;
1903				clocks = <&l4_root_clk_div>;
1904				clock-names = "fck";
1905				status = "disabled";
1906			};
1907		};
1908
1909		epwmss1: epwmss@48440000 {
1910			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1911			reg = <0x48440000 0x30>;
1912			ti,hwmods = "epwmss1";
1913			#address-cells = <1>;
1914			#size-cells = <1>;
1915			status = "disabled";
1916			ranges;
1917
1918			ehrpwm1: pwm@48440200 {
1919				compatible = "ti,dra746-ehrpwm",
1920					     "ti,am3352-ehrpwm";
1921				#pwm-cells = <3>;
1922				reg = <0x48440200 0x80>;
1923				clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1924				clock-names = "tbclk", "fck";
1925				status = "disabled";
1926			};
1927
1928			ecap1: ecap@48440100 {
1929				compatible = "ti,dra746-ecap",
1930					     "ti,am3352-ecap";
1931				#pwm-cells = <3>;
1932				reg = <0x48440100 0x80>;
1933				clocks = <&l4_root_clk_div>;
1934				clock-names = "fck";
1935				status = "disabled";
1936			};
1937		};
1938
1939		epwmss2: epwmss@48442000 {
1940			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1941			reg = <0x48442000 0x30>;
1942			ti,hwmods = "epwmss2";
1943			#address-cells = <1>;
1944			#size-cells = <1>;
1945			status = "disabled";
1946			ranges;
1947
1948			ehrpwm2: pwm@48442200 {
1949				compatible = "ti,dra746-ehrpwm",
1950					     "ti,am3352-ehrpwm";
1951				#pwm-cells = <3>;
1952				reg = <0x48442200 0x80>;
1953				clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
1954				clock-names = "tbclk", "fck";
1955				status = "disabled";
1956			};
1957
1958			ecap2: ecap@48442100 {
1959				compatible = "ti,dra746-ecap",
1960					     "ti,am3352-ecap";
1961				#pwm-cells = <3>;
1962				reg = <0x48442100 0x80>;
1963				clocks = <&l4_root_clk_div>;
1964				clock-names = "fck";
1965				status = "disabled";
1966			};
1967		};
1968
1969		aes1: aes@4b500000 {
1970			compatible = "ti,omap4-aes";
1971			ti,hwmods = "aes1";
1972			reg = <0x4b500000 0xa0>;
1973			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1974			dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1975			dma-names = "tx", "rx";
1976			clocks = <&l3_iclk_div>;
1977			clock-names = "fck";
1978		};
1979
1980		aes2: aes@4b700000 {
1981			compatible = "ti,omap4-aes";
1982			ti,hwmods = "aes2";
1983			reg = <0x4b700000 0xa0>;
1984			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1985			dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1986			dma-names = "tx", "rx";
1987			clocks = <&l3_iclk_div>;
1988			clock-names = "fck";
1989		};
1990
1991		des: des@480a5000 {
1992			compatible = "ti,omap4-des";
1993			ti,hwmods = "des";
1994			reg = <0x480a5000 0xa0>;
1995			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1996			dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
1997			dma-names = "tx", "rx";
1998			clocks = <&l3_iclk_div>;
1999			clock-names = "fck";
2000		};
2001
2002		sham: sham@53100000 {
2003			compatible = "ti,omap5-sham";
2004			ti,hwmods = "sham";
2005			reg = <0x4b101000 0x300>;
2006			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
2007			dmas = <&edma_xbar 119 0>;
2008			dma-names = "rx";
2009			clocks = <&l3_iclk_div>;
2010			clock-names = "fck";
2011		};
2012
2013		rng: rng@48090000 {
2014			compatible = "ti,omap4-rng";
2015			ti,hwmods = "rng";
2016			reg = <0x48090000 0x2000>;
2017			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2018			clocks = <&l3_iclk_div>;
2019			clock-names = "fck";
2020		};
2021	};
2022
2023	thermal_zones: thermal-zones {
2024		#include "omap4-cpu-thermal.dtsi"
2025		#include "omap5-gpu-thermal.dtsi"
2026		#include "omap5-core-thermal.dtsi"
2027		#include "dra7-dspeve-thermal.dtsi"
2028		#include "dra7-iva-thermal.dtsi"
2029	};
2030
2031};
2032
2033&cpu_thermal {
2034	polling-delay = <500>; /* milliseconds */
2035	coefficients = <0 2000>;
2036};
2037
2038&gpu_thermal {
2039	coefficients = <0 2000>;
2040};
2041
2042&core_thermal {
2043	coefficients = <0 2000>;
2044};
2045
2046&dspeve_thermal {
2047	coefficients = <0 2000>;
2048};
2049
2050&iva_thermal {
2051	coefficients = <0 2000>;
2052};
2053
2054&cpu_crit {
2055	temperature = <120000>; /* milli Celsius */
2056};
2057
2058/include/ "dra7xx-clocks.dtsi"
2059